专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07987320B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07987320B2
公开(公告)日：2011-07-26
申请号：US11951783
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

2. 发明授权

US07343455B2 Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation 有权
标题翻译：缓存机制和方法，用于避免对不良受害者选择和回收受害者选择操作
公开(公告)号：US07343455B2
公开(公告)日：2008-03-11
申请号：US11054394
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

3. 发明授权

US07689777B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07689777B2
公开(公告)日：2010-03-30
申请号：US11951770
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

4. 发明申请

US20090150617A1 CACHE MECHANISM AND METHOD FOR AVOIDING CAST OUT ON BAD VICTIM SELECT AND RECYCLING VICTIM SELECT OPERATION 有权
标题翻译：高速缓存机制和方法，用于避免在BAD VICTIM SELECT和RECYCLING VICTIM选择操作
公开(公告)号：US20090150617A1
公开(公告)日：2009-06-11
申请号：US11951783
申请日：2007-12-06
申请人： ROBERT H. BELL, JR. , Guy Lynn Guthrie , William John Starke
发明人： ROBERT H. BELL, JR. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

5. 发明授权

US07401189B2 Pipelining D states for MRU steerage during MRU/LRU member allocation 失效
标题翻译：在MRU / LRU成员分配过程中，管理MRU操纵的D状态
公开(公告)号：US07401189B2
公开(公告)日：2008-07-15
申请号：US11054067
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译：用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。信息被锁存，然后传递给MRU向量生成逻辑。生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

6. 发明授权

US07363433B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07363433B2
公开(公告)日：2008-04-22
申请号：US11054390
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

7. 发明授权

US08352712B2 Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted 失效
标题翻译：方法和系统，用于将处理器发出的存储操作特定发送到存储队列，并发出全信号
公开(公告)号：US08352712B2
公开(公告)日：2013-01-08
申请号：US10840560
申请日：2004-05-06
申请人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3861
摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.
摘要翻译：一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。投机发行的存储操作的副本放置在推测性存储缓冲区内。核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

8. 发明授权

US08195880B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow 有权
标题翻译：信息处理系统，具有双重缓存中的负载操作的即时调度，具有双重调度到写入/读取数据流
公开(公告)号：US08195880B2
公开(公告)日：2012-06-05
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

9. 发明授权

US08015358B2 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US08015358B2
公开(公告)日：2011-09-06
申请号：US12207393
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。

10. 发明授权

US07827354B2 Victim cache using direct intervention 失效
标题翻译：受害者缓存使用直接干预
公开(公告)号：US07827354B2
公开(公告)日：2010-11-02
申请号：US11923952
申请日：2007-10-25
申请人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
发明人： Leo James Clark , James Stephen Fields, Jr. , Guy Lynn Guthrie , Bradley David McCredie , William John Starke
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/127
摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.
摘要翻译：一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式