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1. 发明授权

US07268603B2 Method and apparatus for reducing duty cycle distortion of an output signal 有权
公开(公告)号：US07268603B2
公开(公告)日：2007-09-11
申请号：US11471354
申请日：2006-06-20
申请人： R. Jacob Baker , Timothy B. Cowles
发明人： R. Jacob Baker , Timothy B. Cowles
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/003
摘要： A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

2. 发明授权

US07271635B2 Method and apparatus for reducing duty cycle distortion of an output signal 有权
标题翻译：用于减少输出信号的占空比失真的方法和装置
公开(公告)号：US07271635B2
公开(公告)日：2007-09-18
申请号：US10891535
申请日：2004-07-15
申请人： R. Jacob Baker , Timothy B. Cowles
发明人： R. Jacob Baker , Timothy B. Cowles
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/003
摘要： A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.
摘要翻译：一种用于降低高速设备中的周期信号的占空比失真的方法和装置。更具体地，提供了一种具有切换点调制电路的装置，该切换点调制电路耦合到输入逻辑并且被配置为调制来自输入逻辑的周期性输出信号，使得周期性输出信号以已知电压信号为中心，例如开关点电压信号。

3. 发明授权

US08717220B2 Methods of quantizing signals using variable reference signals 有权
标题翻译：使用可变参考信号量化信号的方法
公开(公告)号：US08717220B2
公开(公告)日：2014-05-06
申请号：US13306868
申请日：2011-11-29
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/56
CPC分类号： G11C16/26 , G11C7/06 , H03M3/39 , H03M3/43 , H03M3/456
摘要： Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.
摘要翻译：读取耦合到电导体的数据位置的方法。计数器从耦合到电导体的模数转换器接收信号。计数器产生两个或多个计数，并且在一些实施例中，计数部分地基于可变参考电压。接口用户可以耦合到计数器的输出。接口用户从计数器接收两个或多个计数，并且基于两个或更多个计数读取由数据位置传送的数据。

4. 发明授权

US08675413B2 Reference current sources 有权
标题翻译：参考电流源
公开(公告)号：US08675413B2
公开(公告)日：2014-03-18
申请号：US13306848
申请日：2011-11-29
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C11/34 , G11C7/02 , G11C7/04
CPC分类号： G11C16/06 , G11C5/147 , G11C7/02 , G11C7/067 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C13/0004 , G11C13/004 , H03M3/39 , H03M3/456 , H04N5/357 , H04N5/376
摘要： Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.
摘要翻译：公开了系统，方法和设备，包括包括第一数据位置，量化电路和参考电流源的电子设备，全部耦合到电导体。参考电流源可以包括具有耦合到电导体的一侧的电流镜和耦合到电流镜的另一侧的第二数据位置。

5. 发明授权

US08582375B2 Methods for sensing memory elements in semiconductor devices 有权
标题翻译：用于感测半导体器件中的存储元件的方法
公开(公告)号：US08582375B2
公开(公告)日：2013-11-12
申请号：US13486535
申请日：2012-06-01
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C5/147 , G11C7/065 , G11C7/16 , G11C8/08 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03M3/43 , H03M3/456
摘要： A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combine (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.
摘要翻译：在某些实施例中，存储器件包括连接到位线的多个存储器元件和可以连接到位线的具有数字输出和模拟输入的Δ-Σ调制器。在一些实施例中，Δ-Σ调制器包括具有第一和第二输入和输出的电路。该电路被配置为组合（加或减）输入信号。第一个输入可以连接到模拟输入。 Δ-Σ调制器还可以包括连接到电路的输出的积分器，具有连接到积分器的输出的输入和连接到数字输出的输出的模数转换器，以及数模转换器，模拟转换器，其输入连接到模数转换器的输出端，输出端连接到电路的第二输入端。

6. 发明授权

US08581168B2 Dual well read-out integrated circuit (ROIC) 有权
标题翻译：双阱读出集成电路（ROIC）
公开(公告)号：US08581168B2
公开(公告)日：2013-11-12
申请号：US13074290
申请日：2011-03-29
申请人： Lloyd F. Linder , Daniel Renner , Michael MacDougal , Jonathan Geske , R. Jacob Baker
发明人： Lloyd F. Linder , Daniel Renner , Michael MacDougal , Jonathan Geske , R. Jacob Baker
IPC分类号： H01L27/00 , G01J1/44
CPC分类号： H04N5/33 , F41G7/008 , F41G7/2253 , F41G7/226 , F41G7/2293 , H04N5/2256
摘要： A single camera capable of capturing high speed laser return pulses for a target, as well as provide imaging information on the background of the target. This capability is enabled by having a read-out integrated circuit (ROIC) capable of extracting both types of information from a pixel of a focal plane array (FPA). Further, an ROIC topology that allows for the ability to distinguish between high frequency and low frequency signal paths, and provide supporting circuitry to process the two paths separately. One path may integrate the low frequency background scene to provide a high fidelity image of the scene. The second path may process high frequency noise and multiple laser pulse returns within a frame. These two paths may be combined to provide a background image with a superimposed laser return.
摘要翻译：一个能够捕获目标的高速激光返回脉冲的单个相机，以及在目标的背景上提供成像信息。通过具有能够从焦平面阵列（FPA）的像素中提取两种类型的信息的读出集成电路（ROIC）来实现该能力。此外，ROIC拓扑允许区分高频和低频信号路径的能力，并提供支持电路来分别处理两个路径。一个路径可以集成低频背景场景以提供场景的高保真图像。第二路径可以处理高频噪声并且在一帧内处理多个激光脉冲返回。这两个路径可以组合以提供具有叠加的激光返回的背景图像。

7. 发明申请

US20120098691A1 QUANTIZING CIRCUITS WITH VARIABLE PARAMETERS 有权
标题翻译：具有可变参数的量化电路
公开(公告)号：US20120098691A1
公开(公告)日：2012-04-26
申请号：US13342844
申请日：2012-01-03
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/34
CPC分类号： H03M1/60 , G11C11/5642 , G11C16/26 , H03K3/0231
摘要： Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.
摘要翻译：用于从数据位置获取数据的系统，方法和设备。该方法可以包括通过在第一条件下感测数据位置来产生第一值，并且通过在第二条件下感测数据位置来产生第二值。该方法还可以包括将第一值与第二值组合以识别由数据位置传送的数据。

8. 发明授权

US08098180B2 Devices including analog-to-digital converters for internal data storage locations 有权
标题翻译：器件包括用于内部数据存储位置的模数转换器
公开(公告)号：US08098180B2
公开(公告)日：2012-01-17
申请号：US12694991
申请日：2010-01-27
申请人： R. Jacob Baker
发明人： R. Jacob Baker
IPC分类号： H03M1/12
CPC分类号： H03M1/504 , G11C7/02 , G11C7/04 , G11C7/1006 , G11C7/16 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C2211/5634 , G11C2211/5644 , H03M3/39 , H03M3/43 , H03M3/456
摘要： A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.
摘要翻译：一种包括耦合到电导体的内部数据存储位置和经由电导体耦合到内部数据存储位置的模拟 - 数字转换器的装置。在一些实施例中，模数转换器包括具有耦合到电导体的输入和耦合到电导体的开关的比较器。

9. 发明申请

US20110261637A1 INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES 有权
标题翻译：通过使用不活泼的BITLINES来增加DRAM-ARRAY
公开(公告)号：US20110261637A1
公开(公告)日：2011-10-27
申请号：US13082785
申请日：2011-04-08
申请人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
发明人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.
摘要翻译：描述了具有增加的通信带宽的存储器件。在该存储器件中，控制逻辑响应于读取命令，使用不活动位线从存储器阵列路由数据信号。然后将这些数据信号放置在相邻的未使用的输入/输出（I / O）线路或路由通道上，而不是正在使用的近似I / O线。例如，位于存储器阵列的顶部和底部的未使用的位线可以用于将数据信号路由到相邻的本地I / O线路。特别地，数据信号可以放置在与相邻位线读出放大器相关联的未使用的本地I / O线上。所产生的增加的通信带宽可以克服由有限数量的本地I / O线在存储器件中施加的约束，而不会明显增加芯片尺寸，功耗或成本。

10. 发明申请

US20110119519A1 METHOD AND APPARATUS FOR PROVIDING SYMMETRICAL OUTPUT DATA FOR A DOUBLE DATA RATE DRAM 失效
标题翻译：用于为双向数据速率DRAM提供对称输出数据的方法和装置
公开(公告)号：US20110119519A1
公开(公告)日：2011-05-19
申请号：US13011191
申请日：2011-01-21
申请人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
发明人： Wen Li , Aaron Schoenfeld , R. Jacob Baker
IPC分类号： G06F1/12
CPC分类号： G11C7/1066 , G06F1/10 , G06F1/12 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , H03L7/0814
摘要： An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.
摘要翻译：公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

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