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1. 发明授权

US08395947B2 Increased DRAM-array throughput using inactive bitlines 有权
标题翻译：使用不稳定位线增加DRAM阵列吞吐量
公开(公告)号：US08395947B2
公开(公告)日：2013-03-12
申请号：US13082785
申请日：2011-04-08
申请人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
发明人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
IPC分类号： G11C7/10
CPC分类号： G11C11/4091 , G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.
摘要翻译：描述了具有增加的通信带宽的存储器件。在该存储器装置中，控制逻辑响应于读取命令，使用不活动位线从存储器阵列路由数据信号。然后将这些数据信号放置在相邻的未使用的输入/输出（I / O）线路或路由通道上，而不是正在使用的近似I / O线。例如，位于存储器阵列的顶部和底部的未使用的位线可以用于将数据信号路由到相邻的本地I / O线路。特别地，数据信号可以放置在与相邻位线读出放大器相关联的未使用的本地I / O线上。所产生的增加的通信带宽可以克服由有限数量的本地I / O线在存储器件中施加的约束，而不会明显增加芯片尺寸，功耗或成本。

2. 发明申请

US20110261637A1 INCREASED DRAM-ARRAY THROUGHPUT USING INACTIVE BITLINES 有权
标题翻译：通过使用不活泼的BITLINES来增加DRAM-ARRAY
公开(公告)号：US20110261637A1
公开(公告)日：2011-10-27
申请号：US13082785
申请日：2011-04-08
申请人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
发明人： Qawi I. Harvard , Robert J. Drost , R. Jacob Baker
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.
摘要翻译：描述了具有增加的通信带宽的存储器件。在该存储器件中，控制逻辑响应于读取命令，使用不活动位线从存储器阵列路由数据信号。然后将这些数据信号放置在相邻的未使用的输入/输出（I / O）线路或路由通道上，而不是正在使用的近似I / O线。例如，位于存储器阵列的顶部和底部的未使用的位线可以用于将数据信号路由到相邻的本地I / O线路。特别地，数据信号可以放置在与相邻位线读出放大器相关联的未使用的本地I / O线上。所产生的增加的通信带宽可以克服由有限数量的本地I / O线在存储器件中施加的约束，而不会明显增加芯片尺寸，功耗或成本。

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