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1. 发明授权

US06681350B2 Method and apparatus for testing memory cells for data retention faults 有权
标题翻译：用于测试存储器单元用于数据保留故障的方法和装置
公开(公告)号：US06681350B2
公开(公告)日：2004-01-20
申请号：US09681602
申请日：2001-05-05
申请人： R. Dean Adams , Aneesha P. Deo , Kamran Zarrineh
发明人： R. Dean Adams , Aneesha P. Deo , Kamran Zarrineh
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/41 , G11C29/08 , G11C29/50016
摘要： A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.
摘要翻译：公开了一种用于测试存储器单元用于数据保持故障的方法。第一逻辑值存储在第一单元中，第二逻辑值存储在存储器件的第二单元中。第二个单元格与第一个单元格共享相同的列。在第二单元可被读取之前，防止与第一和第二单元相关联的位线被预充电。在重复读取第二单元之后，读取第一单元，并且与第一单元和第二单元相关联的位线被预充电。此时，如果第一小区不包含第一逻辑值，则确定数据保留故障已经发生。

2. 发明授权

US06874111B1 System initialization of microcode-based memory built-in self-test 失效
标题翻译：基于微代码的内存系统初始化内置自检
公开(公告)号：US06874111B1
公开(公告)日：2005-03-29
申请号：US09625996
申请日：2000-07-26
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G01R31/28 , G06F12/16 , G11C29/12 , G11C29/16
CPC分类号： G11C29/16 , G11C2029/0401
摘要： The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.
摘要翻译：用于测试集成电路的嵌入式存储器结构的可编程存储器内置自检（BIST）布置的功能被扩展到系统级测试，以在集成电路和包括它们的板被放置在其中之后确定系统的可操作性通过生成在外部测试仪不提供测试指令时加载到指令存储模块中的默认测试信号，可以在更大的系统中进行服务。 BIST安排的这一附加功能可以提高芯片空间利用效率，并提高系统级测试。在芯片制造和/或电路板组装期间从外部测试仪装载测试指令不受影响。

3. 发明授权

US07168005B2 Programable multi-port memory BIST with compact microcode 失效
标题翻译：可编程多端口存储器BIST具有紧凑的微码
公开(公告)号：US07168005B2
公开(公告)日：2007-01-23
申请号：US10354535
申请日：2003-01-30
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G06F11/00
CPC分类号： G06F11/2242 , G11C8/16 , G11C29/16
摘要： A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.
摘要翻译：微代码可编程内置自检（BIST）电路和方法，用于通过多个端口同时或顺序地测试多端口存储器，如微代码指令字所指示的。微代码指令字包含多个可执行子指令和一位信息，用于控制多个子指令中规定的测试操作是并行还是串行执行。可执行子指令由主控制器分派到根据子提示在每个端口执行测试操作的子控制器。微码可编程BIST架构灵活地促进了多个设备，多端口设备的测试，包括多端口存储器结构和复杂的多端口存储器结构。 BIST支持在晶片，模块和老化模式下对存储器的功能进行现场测试，以及系统级测试。

4. 发明授权

US06651201B1 Programmable memory built-in self-test combining microcode and finite state machine self-test 失效
标题翻译：可编程存储器内置自检组合微码和有限状态机自检
公开(公告)号：US06651201B1
公开(公告)日：2003-11-18
申请号：US09626715
申请日：2000-07-26
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G01R3128
CPC分类号： G01R31/3187 , G01R31/2891 , G11C29/16
摘要： A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.
摘要翻译：有限状态机（FSM）用于实时地产生潜在的长序列信号，该序列控制信号的产生，以便在与存储器相同的芯片上的硬件中提供的自检过程期间应用于存储器结构结构体。基于FSM的指令生成器需要比存储相应数量的微代码指令所需的面积少得多的内存自检（BIST）控制器具有模块化架构，允许重新使用硬件设计用于BIST 从而减少了BIST安排的设计成本的消除以适应新的存储器设计。有限状态机在其进行期望的状态序列的操作的顺序性质特别适合于控制对高访问信号的捕获。速度数据传输电路不能适应。

5. 发明授权

US06557127B1 Method and apparatus for testing multi-port memories 失效
标题翻译：用于测试多端口存储器的方法和装置
公开(公告)号：US06557127B1
公开(公告)日：2003-04-29
申请号：US09514870
申请日：2000-02-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C2900
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
摘要翻译：一种用于测试多端口存储器的方法和系统，特别是当一个或多个端口不能直接访问而没有中间逻辑时。该方法和系统将多端口存储器隔离成至少两个部分，然后将其用于测试不能直接访问的一个或多个端口。

6. 发明授权

US07032144B2 Method and apparatus for testing multi-port memories 有权
公开(公告)号：US07032144B2
公开(公告)日：2006-04-18
申请号：US10425003
申请日：2003-04-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

7. 发明授权

US06893154B2 Integrated temperature sensor 有权
标题翻译：集成温度传感器
公开(公告)号：US06893154B2
公开(公告)日：2005-05-17
申请号：US10080037
申请日：2002-02-19
申请人： Spencer M. Gold , Claude R. Gauthier , Brian W. Amick , Kamran Zarrineh , Steven R. Boyle
发明人： Spencer M. Gold , Claude R. Gauthier , Brian W. Amick , Kamran Zarrineh , Steven R. Boyle
IPC分类号： G01K1/02 , G01K7/00 , G01K7/01 , G01K7/32 , G01K11/00
CPC分类号： G01K7/01 , G01K2215/00
摘要： An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.
摘要翻译：提供了一种用于感测集成电路的物理刺激的装置和方法。该装置和方法允许集成电路的精确的管芯温度测量，并且能够提供高精度的管芯温度测量，而不需要独立的电压源或电流源。

8. 发明授权

US07260759B1 Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors 有权
标题翻译：用于高性能微处理器的高效存储器内置自检架构的方法和装置
公开(公告)号：US07260759B1
公开(公告)日：2007-08-21
申请号：US10869698
申请日：2004-06-16
申请人： Kamran Zarrineh , Kenneth A. House , Syed A. Obaidulla
发明人： Kamran Zarrineh , Kenneth A. House , Syed A. Obaidulla
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to be concentrated on the failing memory. The memory BIST architecture is divided into two levels, a memory BIST sequencer level and a satellite memory BIST module. The memory BIST sequencer level includes a set of registers that provide an interface between external agents attempting to communicate with the MBIST module and the Satellite MBIST module.
摘要翻译：存储器BIST架构在外部代理（例如外部测试器和存储器BIST模块）之间提供有效的通信接口。内存BIST架构通过划分搜索空间来减少诊断工作，并允许测试和调试集中在故障存储器上。存储器BIST架构被分为两个级别，一个存储器BIST定序器级和一个卫星存储器BIST模块。存储器BIST定序器级别包括一组寄存器，其提供尝试与MBIST模块和卫星MBIST模块通信的外部代理之间的接口。

9. 发明授权

US07178076B1 Architecture of an efficient at-speed programmable memory built-in self test 有权
标题翻译：高效的可编程存储器的架构内置自检
公开(公告)号：US07178076B1
公开(公告)日：2007-02-13
申请号：US10869720
申请日：2004-06-16
申请人： Kamran Zarrineh , Seokjin Kim
发明人： Kamran Zarrineh , Seokjin Kim
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C2029/0401
摘要： A method of testing an embedded memory at speed within an integrated circuit which includes providing a memory built in self test sequencer module, providing a satellite engine module coupled to the memory built in self test sequencer module and applying a march test to the embedded memory via the satellite engine module based upon information stored within the instruction buffer. The satellite engine module includes an instruction buffer and a sequence generation engine.
摘要翻译：一种在集成电路内以速度测试嵌入式存储器的方法，其包括提供构建在自测序列器模块中的存储器，提供耦合到内置于自测序列器模块中的存储器的卫星引擎模块，并且经由所述卫星引擎模块基于存储在所述指令缓冲器内的信息。卫星引擎模块包括指令缓冲器和序列生成引擎。

10. 发明授权

US06809557B2 Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor 有权
标题翻译：使用片上温度传感器中的线性稳压器增加电源噪声抑制
公开(公告)号：US06809557B2
公开(公告)日：2004-10-26
申请号：US10078130
申请日：2002-02-19
申请人： Claude Gauthier , Spencer Gold , Dean Liu , Kamran Zarrineh , Brian Amick , Pradeep Trivedi
发明人： Claude Gauthier , Spencer Gold , Dean Liu , Kamran Zarrineh , Brian Amick , Pradeep Trivedi
IPC分类号： H03B504
CPC分类号： G05F1/467
摘要： An apparatus that uses a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method for using a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method and apparatus that uses a differential amplifier with a source-follower output stage as a linear voltage regulator for a temperature sensor is provided.
摘要翻译：提供了一种使用线性稳压器来抑制温度传感器中的电源噪声的装置。此外，提供了一种使用线性电压调节器来抑制温度传感器中的电源噪声的方法。此外，提供了一种使用具有源极跟随器输出级的差分放大器作为温度传感器的线性电压调节器的方法和装置。

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