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1. 发明授权

US06874111B1 System initialization of microcode-based memory built-in self-test 失效
标题翻译：基于微代码的内存系统初始化内置自检
公开(公告)号：US06874111B1
公开(公告)日：2005-03-29
申请号：US09625996
申请日：2000-07-26
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G01R31/28 , G06F12/16 , G11C29/12 , G11C29/16
CPC分类号： G11C29/16 , G11C2029/0401
摘要： The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.
摘要翻译：用于测试集成电路的嵌入式存储器结构的可编程存储器内置自检（BIST）布置的功能被扩展到系统级测试，以在集成电路和包括它们的板被放置在其中之后确定系统的可操作性通过生成在外部测试仪不提供测试指令时加载到指令存储模块中的默认测试信号，可以在更大的系统中进行服务。 BIST安排的这一附加功能可以提高芯片空间利用效率，并提高系统级测试。在芯片制造和/或电路板组装期间从外部测试仪装载测试指令不受影响。

2. 发明授权

US07032144B2 Method and apparatus for testing multi-port memories 有权
公开(公告)号：US07032144B2
公开(公告)日：2006-04-18
申请号：US10425003
申请日：2003-04-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

3. 发明授权

US06651201B1 Programmable memory built-in self-test combining microcode and finite state machine self-test 失效
标题翻译：可编程存储器内置自检组合微码和有限状态机自检
公开(公告)号：US06651201B1
公开(公告)日：2003-11-18
申请号：US09626715
申请日：2000-07-26
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G01R3128
CPC分类号： G01R31/3187 , G01R31/2891 , G11C29/16
摘要： A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.
摘要翻译：有限状态机（FSM）用于实时地产生潜在的长序列信号，该序列控制信号的产生，以便在与存储器相同的芯片上的硬件中提供的自检过程期间应用于存储器结构结构体。基于FSM的指令生成器需要比存储相应数量的微代码指令所需的面积少得多的内存自检（BIST）控制器具有模块化架构，允许重新使用硬件设计用于BIST 从而减少了BIST安排的设计成本的消除以适应新的存储器设计。有限状态机在其进行期望的状态序列的操作的顺序性质特别适合于控制对高访问信号的捕获。速度数据传输电路不能适应。

4. 发明授权

US06557127B1 Method and apparatus for testing multi-port memories 失效
标题翻译：用于测试多端口存储器的方法和装置
公开(公告)号：US06557127B1
公开(公告)日：2003-04-29
申请号：US09514870
申请日：2000-02-28
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G11C2900
CPC分类号： G11C29/52 , G11C8/16 , G11C2207/104
摘要： A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
摘要翻译：一种用于测试多端口存储器的方法和系统，特别是当一个或多个端口不能直接访问而没有中间逻辑时。该方法和系统将多端口存储器隔离成至少两个部分，然后将其用于测试不能直接访问的一个或多个端口。

5. 发明授权

US07168005B2 Programable multi-port memory BIST with compact microcode 失效
标题翻译：可编程多端口存储器BIST具有紧凑的微码
公开(公告)号：US07168005B2
公开(公告)日：2007-01-23
申请号：US10354535
申请日：2003-01-30
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Kamran Zarrineh
IPC分类号： G06F11/00
CPC分类号： G06F11/2242 , G11C8/16 , G11C29/16
摘要： A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.
摘要翻译：微代码可编程内置自检（BIST）电路和方法，用于通过多个端口同时或顺序地测试多端口存储器，如微代码指令字所指示的。微代码指令字包含多个可执行子指令和一位信息，用于控制多个子指令中规定的测试操作是并行还是串行执行。可执行子指令由主控制器分派到根据子提示在每个端口执行测试操作的子控制器。微码可编程BIST架构灵活地促进了多个设备，多端口设备的测试，包括多端口存储器结构和复杂的多端口存储器结构。 BIST支持在晶片，模块和老化模式下对存储器的功能进行现场测试，以及系统级测试。

6. 发明授权

US07003704B2 Two-dimensional redundancy calculation 有权
标题翻译：二维冗余计算
公开(公告)号：US07003704B2
公开(公告)日：2006-02-21
申请号：US10292359
申请日：2002-11-12
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Garrett S. Koch
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Garrett S. Koch
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/72
摘要： A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.
摘要翻译：一种用于测试集成电路中的存储器的系统和方法，该集成电路实现BIST测试，以计算行和列冗余，并可以更换有缺陷的行或列的存储单元。该系统包括用于检测一行中的第一单个存储器单元故障的电路; 并记录第一单节故障（SCF）的I / O值。提供电路，用于检测测试行是否发生多于一个单电池故障，并且响应于检测到第二SCF，将后续测试行的记录I / O值与与第一个失败的内存单元。在检测到有缺陷的位时，替换具有相应的缺陷位的存储器的缺陷列和行。

7. 发明授权

US06907554B2 Built-in self test system and method for two-dimensional memory redundancy allocation 失效
标题翻译：内置自检系统和二维内存冗余分配方法
公开(公告)号：US06907554B2
公开(公告)日：2005-06-14
申请号：US10249817
申请日：2003-05-09
申请人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Gary S. Koch
发明人： R. Dean Adams , Thomas J. Eckenrode , Steven L. Gregor , Gary S. Koch
IPC分类号： G11C29/44 , G11C29/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C2029/0401
摘要： A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs. If the greater-than-two detector detects that a word contains more than two SCFs, the built-in self test system identifies the corresponding row as being a must-fix row, since the number of SCFs exceeds the number of redundant columns.
摘要翻译：内置自检系统（124）和二维内存冗余分配方法。所述内置自检系统适于根据需要将两个冗余列（116）和一个冗余行（120）分配给嵌入式存储器（104），以修复行（108）和列（108）中的单个单元故障（SCF）记忆。自检系统包括左优先编码器（136），右优先编码器（140）和大于二检测器（144）。左优先级编码器对最接近相应字最高有效位的第一SCF的位置进行编码。右优先编码器编码最接近对应字的最低有效位的第一SCF的位置。大于2的检测器确定一个单词是否包含两个以上的SCF。如果大于2的检测器检测到一个字含有两个以上的SCF，则内置的自检系统将相应的行识别为必须修复的行，因为SCF的数量超过冗余列的数量。

8. 发明申请

US20090326854A1 TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS 有权
标题翻译：低功耗系统中的测试状态保持逻辑
公开(公告)号：US20090326854A1
公开(公告)日：2009-12-31
申请号：US12147428
申请日：2008-06-26
申请人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna CHAKRAVADHANULA , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G01R31/317
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

9. 发明授权

US08296703B1 Fault modeling for state retention logic 有权
标题翻译：状态保留逻辑的故障建模
公开(公告)号：US08296703B1
公开(公告)日：2012-10-23
申请号：US12339958
申请日：2008-12-19
申请人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
发明人： Krishna Chakravadhanula , Steven L. Gregor , Brion L. Keller , Vivek Chickermane
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G11C29/56008 , G06F2217/78
摘要： A method for modeling state-retention logic includes: specifying a circuit that includes an arrangement of circuit elements, wherein a portion of the circuit is organized into a power domain with a power-domain control for effecting power variations within the power domain, and the power domain includes a state-retention cell that includes a retention element with a retention-element control for saving state-retention-cell values in the retention element during power variations in the power domain; determining one or more pattern faults for detecting defects in state-retention operation of the circuit by associating circuit element values with values for the power-domain control or the retention-element control; and saving one or more values for the one or more pattern faults.
摘要翻译：一种用于建模状态保持逻辑的方法包括：指定包括电路元件布置的电路，其中电路的一部分被组织成具有功率域控制的功率域，以实现功率域内的功率变化，并且功率域包括状态保持单元，其包括具有保持元件控制的保持元件，用于在功率域的功率变化期间在保持元件中保持状态保持单元值; 通过将电路元件值与功率域控制或保持元件控制的值相关联来确定用于检测电路的状态保持操作中的缺陷的一个或多个模式故障; 并为一个或多个模式故障保存一个或多个值。

10. 发明授权

US08271226B2 Testing state retention logic in low power systems 有权
标题翻译：在低功率系统中测试状态保持逻辑
公开(公告)号：US08271226B2
公开(公告)日：2012-09-18
申请号：US12147428
申请日：2008-06-26
申请人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
发明人： Krishna Chakravadhanula , Patrick Gallagher , Vivek Chickermane , Steven L. Gregor , Puneet Arora
IPC分类号： G06F3/00 , G06F3/01 , G06F3/06 , G06F13/10
CPC分类号： G01R31/318575
摘要： A method of testing an Integrated Circuit (IC) includes: loading a sequence of data into a chain of circuit elements that hold data values, where outputs of at least some circuit elements are connected to inputs of adjacent circuit elements so values move sequentially through the chain between a chain input for loading values and a chain output for unloading values, and a first circuit element includes a retention element for saving values during power variations related to the IC. The method further includes: saving a value from the data sequence in the retention element; and accessing the retention element for verifying an accuracy of the saved value from the data sequence.
摘要翻译：一种测试集成电路（IC）的方法包括：将一系列数据加载到保持数据值的电路元件链中，其中至少一些电路元件的输出连接到相邻电路元件的输入，因此值顺序地通过用于装载值的链输入和用于卸载值的链输出之间的链，以及第一电路元件，包括用于在与IC相关的功率变化期间保存值的保持元件。该方法还包括：从保留元素中的数据序列中保存值; 以及访问所述保留元件，以从所述数据序列验证所保存的值的准确性。

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