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1. 发明授权

US07382153B2 On-chip resistor calibration for line termination 有权
标题翻译：用于线路端接的片上电阻校准
公开(公告)号：US07382153B2
公开(公告)日：2008-06-03
申请号：US11459880
申请日：2006-07-25
申请人： Quing Ou-yang , Quan Yu , Ming Qu
发明人： Quing Ou-yang , Quan Yu , Ming Qu
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.
摘要翻译：用于校准集成电路上的电阻值的电路包括电阻网络，参考电压发生器，比较器，伺服环路和移位寄存器。电阻网络包括并联的多个电阻器和开关对。电阻网络还包括与伺服电阻器开关串联的伺服电阻器，使得伺服电阻器和伺服电阻器开关与多个电阻器和开关对并联。伺服环路产生移位寄存器门控信号，并包括用于存储当前比较器输出数据值的当前采样寄存器和用于存储先前比较器输出数据值的先前采样寄存器。移位寄存器在第一状态下接收到移位寄存器选通信号时，输入当前比较器输出数据值以通过移位寄存器移位数据位。

2. 发明申请

US20140003480A1 On Die Jitter Tolerance Test 有权
标题翻译：关于死机容忍测试
公开(公告)号：US20140003480A1
公开(公告)日：2014-01-02
申请号：US13538930
申请日：2012-06-29
申请人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
发明人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
IPC分类号： H04B17/00
CPC分类号： H03L7/087 , G01R29/26 , H03L7/0807 , H03L7/081 , H03L7/0998 , H04B17/104 , H04L1/205 , H04L1/243 , H04L7/033
摘要： A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.
摘要翻译：公开了一种用于执行裸片抖动容限测试的系统和方法。基于输入信号产生一组时钟。该组时钟包括基于输入信号的数据切换沿的同相信号。此外，该组时钟包括偏移180度的反相时钟相位和一对相位偏移一定数量度θ的时钟。基于反相时钟和两个相移时钟对数据输入进行采样。可以基于反相时钟和两个相移时钟中的每一个是否以各种θ值从输入信号中采样正确的数据来确定输入信号的开眼。

3. 发明申请

US20080061837A1 Low Supply Voltage, Large Output Swing, Source-Terminated Output Driver for High Speed AC-coupled Double-Termination Serial Links 审中-公开
标题翻译：低电源电压，大输出摆幅，源极端接输出驱动器，用于高速交流耦合双端子串行链路
公开(公告)号：US20080061837A1
公开(公告)日：2008-03-13
申请号：US11467528
申请日：2006-08-25
申请人： Feng Xu , Quan Yu , Ming Qu
发明人： Feng Xu , Quan Yu , Ming Qu
IPC分类号： H03K19/086
CPC分类号： H03K19/018528
摘要： A current mode logic circuit includes a current mode logic driver circuit and a transistor biasing improvement circuit. The transistor biasing improvement circuit includes a first current source coupled to a first output node of the current mode logic driver circuit and a second current source coupled to a second output node of the current mode logic driver circuit. The first current source and the second current source raise a common mode voltage at the first output node and the second output node.
摘要翻译：电流模式逻辑电路包括电流模式逻辑驱动器电路和晶体管偏置改善电路。晶体管偏置改善电路包括耦合到电流模式逻辑驱动器电路的第一输出节点的第一电流源和耦合到当前模式逻辑驱动器电路的第二输出节点的第二电流源。第一电流源和第二电流源在第一输出节点和第二输出节点处提高共模电压。

4. 发明申请

US20080024172A1 Actively Compensated Buffering for High Speed Current Mode Logic Data Path 审中-公开
标题翻译：用于高速电流模式逻辑数据通道的积极补偿缓冲
公开(公告)号：US20080024172A1
公开(公告)日：2008-01-31
申请号：US11460122
申请日：2006-07-26
申请人： Quan Yu , Ming Qu
发明人： Quan Yu , Ming Qu
IPC分类号： H03K19/094
CPC分类号： H03K19/01707 , H03F1/483 , H03F3/45183 , H03F2200/36 , H03F2203/45248 , H03F2203/45318 , H03F2203/45352 , H03F2203/45374 , H03F2203/45638 , H03F2203/45702 , H03K19/018514
摘要： An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.
摘要翻译：积极补偿的CML电路包括CML缓冲电路和带宽扩展电路。 CML缓冲电路包括第一MOS晶体管和差分对配置中的第二MOS晶体管。第一负载电阻器在第一输出端耦合到第一MOS晶体管漏极，第二负载电阻器在第二输出端子耦合到第二MOS晶体管漏极。带宽扩展电路以源跟随器配置耦合到CML缓冲电路。带宽扩展电路包括第三MOS晶体管和第四MOS晶体管。电容器耦合在第三MOS晶体管源极和第四MOS晶体管源极之间。第四MOS晶体管和第三MOS晶体管在第一输出端和第二输出端产生高通功能。

5. 发明授权

US08923375B2 On die jitter tolerance test 有权
标题翻译：裸片抖动容限测试
公开(公告)号：US08923375B2
公开(公告)日：2014-12-30
申请号：US13538930
申请日：2012-06-29
申请人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
发明人： Ming Qu , Yuanping Chen , Yuntao Zhu , Quan Yu , Kochung Lee
IPC分类号： H04B17/00
CPC分类号： H03L7/087 , G01R29/26 , H03L7/0807 , H03L7/081 , H03L7/0998 , H04B17/104 , H04L1/205 , H04L1/243 , H04L7/033
摘要： A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.
摘要翻译：公开了一种用于执行裸片抖动容限测试的系统和方法。基于输入信号产生一组时钟。该组时钟包括基于输入信号的数据切换沿的同相信号。此外，该组时钟包括一个偏移180度的反相时钟相位和一对相位正负偏移一定数量的时钟。基于反相时钟和两个相移时钟对数据输入进行采样。输入信号的开眼可以基于每个反相时钟和两个相移时钟从各种输入信号中的输入信号中得到正确的数据来确定; 价值观。

6. 发明申请

US20080024160A1 On-Chip Resistor Calibration For Line Termination 有权
标题翻译：用于线路端接的片上电阻校准
公开(公告)号：US20080024160A1
公开(公告)日：2008-01-31
申请号：US11459880
申请日：2006-07-25
申请人： Qing Ou-yang , Quan Yu , Ming Qu
发明人： Qing Ou-yang , Quan Yu , Ming Qu
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： Systems and methods for on-chip resistor calibration are disclosed. A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register. A data output of each flip flop of the shift register is coupled to and controls an associated controllable switch at the plurality of resistor and switch pairs.
摘要翻译：公开了用于片上电阻校准的系统和方法。用于校准集成电路上的电阻值的电路包括电阻网络，参考电压发生器，比较器，伺服环路和移位寄存器。电阻网络包括并联的多个电阻器和开关对。电阻网络还包括与伺服电阻器开关串联的伺服电阻器，使得伺服电阻器和伺服电阻器开关与多个电阻器和开关对并联。伺服环路产生移位寄存器门控信号，并包括用于存储当前比较器输出数据值的当前采样寄存器和用于存储先前比较器输出数据值的先前采样寄存器。移位寄存器在第一状态下接收到移位寄存器选通信号时，输入当前比较器输出数据值以通过移位寄存器移位数据位。移位寄存器的每个触发器的数据输出耦合到并控制多个电阻器和开关对上的相关联的可控开关。

7. 发明授权

US08610479B2 On die low power high accuracy reference clock generation 有权
标题翻译：低功耗高精度基准时钟生成
公开(公告)号：US08610479B2
公开(公告)日：2013-12-17
申请号：US13276269
申请日：2011-10-18
申请人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
发明人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
IPC分类号： G06F1/04
CPC分类号： H03L7/22
摘要： A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.
摘要翻译：公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。在未知的初始频率的芯片上产生RCO时钟。比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。发送信号，导致RCO电路中的电流源或电容器被修改。因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

8. 发明申请

US20130093466A1 ON DIE LOW POWER HIGH ACCURACY REFERENCE CLOCK GENERATION 有权
标题翻译： ON DIE低功率高精度参考时钟产生
公开(公告)号：US20130093466A1
公开(公告)日：2013-04-18
申请号：US13276269
申请日：2011-10-18
申请人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
发明人： Kochung Lee , Quan Yu , Yuntao Zhu , Lei Xie , Ming Qu
IPC分类号： H03D13/00
CPC分类号： H03L7/22
摘要： A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.
摘要翻译：公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。在未知的初始频率的芯片上产生RCO时钟。比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。发送信号，导致RCO电路中的电流源或电容器被修改。因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

9. 发明申请

US20110150055A1 Active Auxiliary Channel Buffering 有权
标题翻译：主动辅助通道缓冲
公开(公告)号：US20110150055A1
公开(公告)日：2011-06-23
申请号：US12645240
申请日：2009-12-22
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04B1/38
CPC分类号： G09G5/006 , G09G2330/021 , G09G2350/00 , G09G2370/045 , G09G2370/10 , H04L65/4023 , H04L65/4092 , H04L67/34
摘要： A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.
摘要翻译：描述用于在源设备和宿之间传送配置数据的系统和方法。主动缓冲器从辅助通信信道接收数据，该辅助通信信道在源设备和宿设备之间传送数据。主动缓冲器修改从辅助通信信道接收到的数据。例如，有源缓冲器放大所接收的数据或电接收数据。然后将修改的数据从活动缓冲器发送到目的地设备。在一个实施例中，辅助通信信道是双向的，并且在从第一设备接收数据时，主动缓冲器被修改以允许将数据从第一设备单向传输到第二设备。

10. 发明授权

US07224213B2 Switched capacitor ripple-smoothing filter 有权
标题翻译：开关电容纹波平滑滤波器
公开(公告)号：US07224213B2
公开(公告)日：2007-05-29
申请号：US10841987
申请日：2004-05-07
申请人： Xiang Zhu , Ming Qu
发明人： Xiang Zhu , Ming Qu
IPC分类号： H03K5/00
CPC分类号： H03L7/0893 , H03H19/004 , H03L7/093
摘要： A switched-capacitor ripple-smoothing filter includes a first pair of capacitors. The filter is configured such that either capacitor in the first pair may be reset and have a terminal coupled to a first input port and such that the remaining capacitor in the first pair is isolated from the first input port and has the terminal coupled to a first output port while the other capacitor is being charged. The filter further includes a second pair of capacitors, the filter being configured such that either capacitor in the second pair may be reset and have a terminal coupled to a second input port and such that the remaining capacitor in the second pair is isolated from the second input port and has the terminal coupled to a second output port while the other capacitor in the second pair is being charged. Advantageously, the filter is configured such that the capacitors in the first and second pair are reset responsive to the assertion of a single reset signal.
摘要翻译：开关电容波纹平滑滤波器包括第一对电容器。滤波器被配置为使得第一对中的任一电容器可以被复位并且具有耦合到第一输入端口的端子，并且使得第一对中的剩余电容器与第一输入端口隔离，并且将端子耦合到第一输出端口，而另一个电容器正在充电。滤波器还包括第二对电容器，滤波器被配置为使得第二对中的电容器可以被复位并且具有耦合到第二输入端口的端子，并且使得第二对中的剩余电容器与第二对隔离输入端口，并且其端子耦合到第二输出端口，而第二对中的另一个电容器被充电。有利地，滤波器被配置为使得响应于单个复位信号的断言来复位第一和第二对中的电容器。

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