专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06528855B2 MOSFET having a low aspect ratio between the gate and the source/drain 失效
标题翻译： MOSFET在栅极和源极/漏极之间具有低的纵横比
公开(公告)号：US06528855B2
公开(公告)日：2003-03-04
申请号：US09911894
申请日：2001-07-24
申请人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
发明人： Qiuyi Ye , William Tonti , Yujun Li , Jack A. Mandelman
IPC分类号： H01L29772
CPC分类号： H01L29/0653 , H01L21/823814 , H01L21/823878 , H01L29/66621 , H01L29/66636 , H01L29/7834
摘要： A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.
摘要翻译：具有新的源极/漏极（S / D）结构的MOSFET特别适用于现代CMOS技术的较小特征尺寸。 S / D导体位于浅沟槽隔离（STI）上，以实现低结漏电和低结电容。通过STI蚀刻步骤（根据制造MOSFET的第一种方法）或硅蚀刻步骤（根据制造MOSFET的第二种方法）限定S / D结深度。通过控制蚀刻深度，实现非常浅的结深度。栅极长度的变化很小，因为栅极区域是通过蚀刻晶体硅来定义的，而不是蚀刻多晶硅。由于栅极导体和源极和漏极导体在同一个电平上对齐，栅极和S / D之间的纵横比较低。自杀技术应用于源极和漏极，用于低寄生电阻; 然而，这不会导致严重的S / D结泄漏，因为源极和漏极导体位于STI上。

2. 发明申请

US20050199966A1 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
标题翻译：具有无边界接触的双功能半导体结构及其制造方法
公开(公告)号：US20050199966A1
公开(公告)日：2005-09-15
申请号：US11098103
申请日：2005-04-04
申请人： Qiuyi Ye , William Tonti , Yujun Li
发明人： Qiuyi Ye , William Tonti , Yujun Li
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
摘要翻译：提出了一种具有无边界接触的双功能半导体结构及其制造方法。该结构可以包括具有基本无帽栅极的场效应晶体管（FET）和与无盖栅极相邻的扩散部的导电接触，其中导电触点与栅极无边界。由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。

3. 发明授权

US06908815B2 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
公开(公告)号：US06908815B2
公开(公告)日：2005-06-21
申请号：US10624781
申请日：2003-07-22
申请人： Qiuyi Ye , William R. Tonti , Yujun Li
发明人： Qiuyi Ye , William R. Tonti , Yujun Li
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L21/336
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

4. 发明授权

US06642584B2 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
公开(公告)号：US06642584B2
公开(公告)日：2003-11-04
申请号：US09772630
申请日：2001-01-30
申请人： Qiuyi Ye , William R. Tonti , Yujun Li
发明人： Qiuyi Ye , William R. Tonti , Yujun Li
IPC分类号： H01L2978
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

5. 发明授权

US07015552B2 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
公开(公告)号：US07015552B2
公开(公告)日：2006-03-21
申请号：US11098103
申请日：2005-04-04
申请人： Qiuyi Ye , William R. Tonti , Yujun Li
发明人： Qiuyi Ye , William R. Tonti , Yujun Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.

6. 发明授权

US06444548B1 Bitline diffusion with halo for improved array threshold voltage control 有权
公开(公告)号：US06444548B1
公开(公告)日：2002-09-03
申请号：US09257817
申请日：1999-02-25
申请人： Ramachandra Divakaruni , Yujun Li , Jack A. Mandelman
发明人： Ramachandra Divakaruni , Yujun Li , Jack A. Mandelman
IPC分类号： H01L218242
摘要： A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

7. 发明授权

US06348394B1 Method and device for array threshold voltage control by trapped charge in trench isolation 失效
标题翻译：用于沟槽隔离中捕获电荷的阵列阈值电压控制的方法和装置
公开(公告)号：US06348394B1
公开(公告)日：2002-02-19
申请号：US09573375
申请日：2000-05-18
申请人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
发明人： Jack A. Mandelman , Rama Divakaruni , Herbert Ho , Giuseppe La Rosa , Yujun Li , Jochen Beintner , Radhika Srinivasan
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.
摘要翻译：提供半导体器件及其制造方法。在半导体衬底中形成沟槽。优选在沟槽的表面上形成薄的氧化物衬垫。氮化物衬垫形成在沟槽中。电荷被困在氮化物衬垫中。在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。优选地，氧化物填充物直接形成在氮化物衬垫上。

8. 发明授权

US09235879B2 Apparatus, system, and method for temporal domain hole filling based on background modeling for view synthesis 有权
标题翻译：基于视图合成的背景建模的时域填充的装置，系统和方法
公开(公告)号：US09235879B2
公开(公告)日：2016-01-12
申请号：US13538966
申请日：2012-06-29
申请人： Sun Wenxiu , Oscar C. Au , Lingfeng Xu , Yujun Li , Wei Hu , Lu Wang
发明人： Sun Wenxiu , Oscar C. Au , Lingfeng Xu , Yujun Li , Wei Hu , Lu Wang
IPC分类号： G06T5/00 , H04N13/02
CPC分类号： G06T5/005 , G06T2207/10021 , G06T2207/20182 , H04N13/261
摘要： Embodiments of apparatuses, systems, and methods for a temporal hole filling are described. Specifically, an embodiment of the present invention may include a depth-based hole filling process that includes a background modeling technique (SGM). Beneficially, in such an embodiment, holes in the synthesized view may be filled effectively and efficiently.
摘要翻译：描述了用于时空填充的装置，系统和方法的实施例。具体地，本发明的实施例可以包括基于深度的孔填充过程，其包括背景建模技术（SGM）。有利地，在这样的实施例中，可以有效且有效地填充合成视图中的孔。

9. 发明授权

US07696539B2 Device fabrication by anisotropic wet etch 失效
标题翻译：通过各向异性湿法蚀刻的器件制造
公开(公告)号：US07696539B2
公开(公告)日：2010-04-13
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer, Jr. , Jochen Beintner
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

10. 发明授权

US07470570B2 Process for fabrication of FinFETs 有权
标题翻译： FinFET的制造工艺
公开(公告)号：US07470570B2
公开(公告)日：2008-12-30
申请号：US11559460
申请日：2006-11-14
申请人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
发明人： Jochen Beintner , Gary B. Bronner , Ramachandra Divakaruni , Yujun Li
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.
摘要翻译：提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式