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    • 6. 发明申请
    • Low leakage heterojunction vertical transistors and high performance devices thereof
    • 低漏极异质结垂直晶体管及其高性能器件
    • US20070148939A1
    • 2007-06-28
    • US11317285
    • 2005-12-22
    • Jack ChuQiqing Ouyang
    • Jack ChuQiqing Ouyang
    • H01L21/3205
    • H01L21/823885H01L21/823807H01L29/045H01L29/161H01L29/165H01L29/778H01L29/7781H01L29/7782H01L29/7789H01L29/7828H01L29/7848H01L29/78642
    • A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
    • 描述了一种用于形成场效应晶体管,场效应晶体管和CMOS电路的垂直沟道结构的方法,其在垂直单晶半导体结构的侧壁上结合有漏极,主体和源极区域,其中异质结为 形成在晶体管的源极和主体之间,其中源极区域和沟道独立地相对于体区域进行晶格应变,并且其中漏极区域包含碳掺杂区域以防止掺杂剂(即,B和P)扩散到 身体。 本发明减少了短沟道效应的问题,例如漏极引起的栅极降低和从源极到漏极区域的漏电流经由异质结,并且同时独立地允许沟道区域中的晶格应变,以通过选择半导体材料增加迁移率。 栅极长度低于100nm的可扩展性的问题通过源极和体区之间的异质结来克服。