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1. 发明授权

US09306004B2 SiC devices with high blocking voltage terminated by a negative bevel 有权
公开(公告)号：US09306004B2
公开(公告)日：2016-04-05
申请号：US13108366
申请日：2011-05-16
申请人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
发明人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/06 , H01L29/10 , H01L29/36 , H01L29/732 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/861 , H01L29/16
摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

2. 发明申请

US20130062723A1 SCHOTTKY DIODE 有权
公开(公告)号：US20130062723A1
公开(公告)日：2013-03-14
申请号：US13229749
申请日：2011-09-11
申请人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
发明人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/8611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2224/05552
摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

3. 发明申请

US20130062619A1 EDGE TERMINATION STRUCTURE EMPLOYING RECESSES FOR EDGE TERMINATION ELEMENTS 有权
标题翻译：边缘终止结构使用边缘终止元素的边缘
公开(公告)号：US20130062619A1
公开(公告)日：2013-03-14
申请号：US13229750
申请日：2011-09-11
申请人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
发明人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0661 , H01L29/8611 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2224/05552
摘要： Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.
摘要翻译：边缘终端结构的元件，例如多个同心保护环，是漂移层中的有效掺杂区域。为了增加这些掺杂区域的深度，可以在要形成边缘终端结构的元件的漂移层的表面中形成各自的凹部。一旦凹陷形成在漂移层中，凹槽周围和底部的这些区域被掺杂以形成相应的边缘终端元件。

4. 发明申请

US20120292636A1 SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL 有权
标题翻译：具有高阻塞电压的SIC器件由负极水平端接
公开(公告)号：US20120292636A1
公开(公告)日：2012-11-22
申请号：US13108366
申请日：2011-05-16
申请人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
发明人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/161
CPC分类号： H01L29/7813 , H01L21/0465 , H01L29/0615 , H01L29/0661 , H01L29/1004 , H01L29/1016 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/732 , H01L29/7397 , H01L29/74 , H01L29/861
摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
摘要翻译：公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。在一个实施例中，期望的斜率小于或等于十五度。在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET）或PIN二极管。

5. 发明授权

US08211770B2 Transistor with A-face conductive channel and trench protecting well region 有权
标题翻译：具有A面导电沟道和沟槽保护阱区的晶体管
公开(公告)号：US08211770B2
公开(公告)日：2012-07-03
申请号：US13167806
申请日：2011-06-24
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

6. 发明申请

US20090315036A1 SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING DOPED REGIONS ARRANGED AS ISLANDS AND METHODS OF FABRICATING SAME 有权
标题翻译：半导体器件包括具有安置区域的肖特基二极体和其制造方法
公开(公告)号：US20090315036A1
公开(公告)日：2009-12-24
申请号：US12492670
申请日：2009-06-26
申请人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
发明人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L29/872 , H01L29/24 , H01L21/329
CPC分类号： H01L29/0619 , H01L21/046 , H01L29/0615 , H01L29/1608 , H01L29/6606 , H01L29/872
摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.
摘要翻译：根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。多个间隔开的第一掺杂区域被布置在有源区域内。多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。多个第一掺杂区域在半导体层中被布置为岛状。半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。

7. 发明授权

US09064710B2 Transistor with A-face conductive channel and trench protecting well region 有权
标题翻译：具有A面导电沟道和沟槽保护阱区的晶体管
公开(公告)号：US09064710B2
公开(公告)日：2015-06-23
申请号：US13482311
申请日：2012-05-29
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L29/66 , H01L29/06 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/16
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流以形成AMOSFET，其在导通状态下的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

8. 发明授权

US09337268B2 SiC devices with high blocking voltage terminated by a negative bevel 有权
标题翻译：具有高阻断电压的SiC器件由负斜角端接
公开(公告)号：US09337268B2
公开(公告)日：2016-05-10
申请号：US13108366
申请日：2011-05-16
申请人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
发明人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/06 , H01L29/10 , H01L29/36 , H01L29/732 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/861 , H01L29/16
CPC分类号： H01L29/7813 , H01L21/0465 , H01L29/0615 , H01L29/0661 , H01L29/1004 , H01L29/1016 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/732 , H01L29/7397 , H01L29/74 , H01L29/861
摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.
摘要翻译：公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。在一个实施例中，期望的斜率小于或等于十五度。在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET）或PIN二极管。

9. 发明授权

US08809904B2 Electronic device structure with a semiconductor ledge layer for surface passivation 有权
标题翻译：具有用于表面钝化的半导体凸缘层的电子器件结构
公开(公告)号：US08809904B2
公开(公告)日：2014-08-19
申请号：US12843113
申请日：2010-07-26
申请人： Qingchun Zhang , Anant Agarwal
发明人： Qingchun Zhang , Anant Agarwal
IPC分类号： H01L29/36
CPC分类号： H01L29/66378 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/66234 , H01L29/66363 , H01L29/744
摘要： Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
摘要翻译：公开了包括用于表面钝化的半导体凸缘层的电子器件结构及其制造方法。在一个实施例中，电子器件包括具有交替掺杂类型的期望半导体材料的多个半导体层。半导体层包括第一掺杂类型的基极层，其包括形成电子器件的第一接触区域的高度掺杂的阱和在基底层上的第二掺杂类型的一个或多个接触层，其被蚀刻以形成第二掺杂阱电子设备的接触区域。一个或多个接触层的蚀刻在基层的表面上引起显着的晶体损伤，并因此导致界面电荷。为了钝化基底层的表面，半导体材料的半导体凸缘层至少在基底层的表面上外延生长。

10. 发明授权

US08330244B2 Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same 有权
标题翻译：包括具有排列成岛的掺杂区域的肖特基二极管的半导体器件及其制造方法
公开(公告)号：US08330244B2
公开(公告)日：2012-12-11
申请号：US12492670
申请日：2009-06-26
申请人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
发明人： Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07
CPC分类号： H01L29/0619 , H01L21/046 , H01L29/0615 , H01L29/1608 , H01L29/6606 , H01L29/872
摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.
摘要翻译：根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。多个间隔开的第一掺杂区域被布置在有源区域内。多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。多个第一掺杂区域在半导体层中被布置为岛状。半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。

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