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1. 发明授权

US08211770B2 Transistor with A-face conductive channel and trench protecting well region 有权
标题翻译：具有A面导电沟道和沟槽保护阱区的晶体管
公开(公告)号：US08211770B2
公开(公告)日：2012-07-03
申请号：US13167806
申请日：2011-06-24
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

2. 发明授权

US09064710B2 Transistor with A-face conductive channel and trench protecting well region 有权
标题翻译：具有A面导电沟道和沟槽保护阱区的晶体管
公开(公告)号：US09064710B2
公开(公告)日：2015-06-23
申请号：US13482311
申请日：2012-05-29
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L29/66 , H01L29/06 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/16
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流以形成AMOSFET，其在导通状态下的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

3. 发明申请

US20110250737A1 TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION 有权
标题翻译：具有导通通道和保护区域的晶体管
公开(公告)号：US20110250737A1
公开(公告)日：2011-10-13
申请号：US13167806
申请日：2011-06-24
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L21/20
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

4. 发明申请

US20120235164A1 TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION 审中-公开
标题翻译：具有导通通道和保护区域的晶体管
公开(公告)号：US20120235164A1
公开(公告)日：2012-09-20
申请号：US13482311
申请日：2012-05-29
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L29/16 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

5. 发明授权

US07989882B2 Transistor with A-face conductive channel and trench protecting well region 有权
标题翻译：具有A面导电沟道和沟槽保护阱区的晶体管
公开(公告)号：US07989882B2
公开(公告)日：2011-08-02
申请号：US11952447
申请日：2007-12-07
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

6. 发明申请

US20090146154A1 Transistor with A-Face Conductive Channel and Trench Protecting Well Region 有权
标题翻译：具有A面导电沟道和沟槽保护区的晶体管
公开(公告)号：US20090146154A1
公开(公告)日：2009-06-11
申请号：US11952447
申请日：2007-12-07
申请人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
发明人： Qingchun Zhang , Anant Agarwal , Charlotte Jonas
IPC分类号： H01L29/24 , H01L29/78 , H01L29/74 , H01L21/04
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0615 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/749 , H01L29/7828
摘要： A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.
摘要翻译：晶体管结构优化沿着碳化硅本体的A面的电流，以形成AMOSFET，其在导通状态的正向导通期间使漂移区域中的JFET效应最小化。由于添加了在沟槽门控器件中保护栅极角区域的高掺杂阱区域，AMOSFET进一步显示出高电压阻断能力。除了在限定沟槽的半导体台面的部分上延伸的掩埋沟道层之外，AMOSFET还沿着沟槽侧壁使用A面导电。掺杂阱从至少一个台面延伸到电流扩散层内的深度大于沟槽的深度。电流扩展层在沟槽底部下方的半导体台面之间延伸，以降低导通状态下的结电阻。沟槽与深井之间的缓冲层进一步提供了防止沟渠角落处的场地挤压的保护。

7. 发明授权

US09142662B2 Field effect transistor devices with low source resistance 有权
标题翻译：具有低源电阻的场效应晶体管器件
公开(公告)号：US09142662B2
公开(公告)日：2015-09-22
申请号：US13108440
申请日：2011-05-16
申请人： Sei-Hyung Ryu , Doyle Craig Capell , Lin Cheng , Sarit Dhar , Charlotte Jonas , Anant Agarwal , John Palmour
发明人： Sei-Hyung Ryu , Doyle Craig Capell , Lin Cheng , Sarit Dhar , Charlotte Jonas , Anant Agarwal , John Palmour
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739 , H01L29/04 , H01L29/16
CPC分类号： H01L29/7802 , H01L29/045 , H01L29/0696 , H01L29/1608 , H01L29/7395
摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.
摘要翻译：半导体器件包括具有第一导电类型的漂移层，漂移层中具有与第一导电类型相反的第二导电类型的阱区以及阱区中的源极区。源极区具有第一导电类型并且限定在井区域中的通道区域。源极区域包括与沟道区域相邻的横向源极区域和远离与沟道区域相对的横向源极区域延伸的多个源极接触区域。具有第二导电类型的体接触区域在多个源极接触区域中的至少两个之间并且与阱区域接触。源欧姆触点与源极接触区域和身体接触区域中的至少一个重叠。半导体器件的源极接触区域的最小尺寸由源极欧姆接触和至少一个源极接触区域之间的重叠区域限定。

8. 发明授权

US09306004B2 SiC devices with high blocking voltage terminated by a negative bevel 有权
公开(公告)号：US09306004B2
公开(公告)日：2016-04-05
申请号：US13108366
申请日：2011-05-16
申请人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
发明人： Qingchun Zhang , Craig Capell , Anant Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/06 , H01L29/10 , H01L29/36 , H01L29/732 , H01L29/739 , H01L29/74 , H01L29/78 , H01L29/861 , H01L29/16
摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

9. 发明申请

US20130062723A1 SCHOTTKY DIODE 有权
公开(公告)号：US20130062723A1
公开(公告)日：2013-03-14
申请号：US13229749
申请日：2011-09-11
申请人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
发明人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/8611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2224/05552
摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

10. 发明申请

US20130062619A1 EDGE TERMINATION STRUCTURE EMPLOYING RECESSES FOR EDGE TERMINATION ELEMENTS 有权
标题翻译：边缘终止结构使用边缘终止元素的边缘
公开(公告)号：US20130062619A1
公开(公告)日：2013-03-14
申请号：US13229750
申请日：2011-09-11
申请人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
发明人： Jason Patrick Henning , Qingchun Zhang , Sei-Hyung Ryu , Anant Agarwal , John Williams Palmour , Scott Allen
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0661 , H01L29/8611 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/00 , H01L2224/05552
摘要： Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.
摘要翻译：边缘终端结构的元件，例如多个同心保护环，是漂移层中的有效掺杂区域。为了增加这些掺杂区域的深度，可以在要形成边缘终端结构的元件的漂移层的表面中形成各自的凹部。一旦凹陷形成在漂移层中，凹槽周围和底部的这些区域被掺杂以形成相应的边缘终端元件。

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