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1. 发明授权

US09379090B1 System, apparatus, and method for split die interconnection 有权
标题翻译：用于分离管芯互连的系统，装置和方法
公开(公告)号：US09379090B1
公开(公告)日：2016-06-28
申请号：US14622346
申请日：2015-02-13
申请人： QUALCOMM Incorporated
发明人： Ahmer Raza Syed , Chin-Kwan Kim , Omar James Bchir , Milind Pravin Shah , Ryan David Lane
IPC分类号： H01L23/34 , H01L25/065 , H01L23/538 , H01L23/367 , H01L23/00 , H01L21/683 , H01L25/00
CPC分类号： H01L25/0655 , H01L21/4857 , H01L21/6835 , H01L23/13 , H01L23/145 , H01L23/36 , H01L23/49816 , H01L23/5383 , H01L23/5385 , H01L24/32 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2221/68372 , H01L2224/32225 , H01L2224/73253 , H01L2224/81005 , H01L2224/83191 , H01L2224/92225 , H01L2924/15158 , H01L2924/15333
摘要： A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.
摘要翻译：用于并排管芯构造的半导体封装可以包括具有空腔的衬底，位于空腔内的桥插入器，并且具有面向第一管芯和第二管芯的主动侧的有源侧，并且部分水平地与第一管芯重叠，第二模具以提供第一模具和第二模具之间的互连，以及附接到第一模具和第二模具的背面的热元件，以为第一模具和第二模具提供热路径和热存储。

2. 发明授权

US09355898B2 Package on package (PoP) integrated device comprising a plurality of solder resist layers 有权
标题翻译：封装的封装（PoP）集成器件包括多个阻焊层
公开(公告)号：US09355898B2
公开(公告)日：2016-05-31
申请号：US14447399
申请日：2014-07-30
申请人： QUALCOMM Incorporated
发明人： Rajneesh Kumar , Houssam Wafic Jomaa , David Fraser Rae , Layal Rouhana , Omar James Bchir
IPC分类号： H01L23/48 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/495 , H01L21/48 , H01L23/498
CPC分类号： H01L21/76852 , H01L21/4825 , H01L21/76879 , H01L23/4952 , H01L23/49527 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/528 , H01L23/53204 , H01L2224/16227 , H01L2224/16238 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/00014
摘要： Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
摘要翻译：一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口，开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。在一些实施方案中，开口至少部分地填充有导电材料。导电材料包括焊料和/或互连中的一种。集成器件包括耦合到导电材料的第一互连。第一互连是至少焊料和/或互连球之一。在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

3. 发明申请

US20150116965A1 EMBEDDED BRIDGE STRUCTURE IN A SUBSTRATE 有权
标题翻译：嵌入桥梁结构在基板上
公开(公告)号：US20150116965A1
公开(公告)日：2015-04-30
申请号：US14067677
申请日：2013-10-30
申请人： Qualcomm Incorporated
发明人： Chin-Kwan Kim , Omar James Bchir , Dong Wook Kim , Hong Bok We
IPC分类号： H05K1/18 , H05K1/11
CPC分类号： H05K1/18 , H01L23/5383 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/15192 , H01L2924/15313 , H05K1/11 , H01L2924/014
摘要： Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.
摘要翻译：一些新颖的特征涉及包括第一介电层和桥结构的基板。桥结构嵌入在第一电介质层中。桥结构构造成在第一管芯和第二管芯之间提供电连接。第一和第二管芯被配置为耦合到衬底。桥结构包括第一组互连和第二介电层。第一组互连嵌入在第一介质层中。在一些实现中，桥结构还包括第二组互连。在一些实施方案中，第二介电层被嵌入在第一介电层中。在一些实施方式中，第一介电层包括桥结构的第一组互连，桥结构中的第二组互连以及桥结构中的一组焊盘。

4. 发明授权

US09370097B2 Package substrate with testing pads on fine pitch traces 有权
标题翻译：封装衬底，测试垫在细间距迹线上
公开(公告)号：US09370097B2
公开(公告)日：2016-06-14
申请号：US13783168
申请日：2013-03-01
申请人： QUALCOMM Incorporated
发明人： Chin-Kwan Kim , Kuiwon Kang , Omar James Bchir
IPC分类号： H05K7/10 , H05K1/11 , G01R31/28 , H05K1/02 , H05K3/34
CPC分类号： H05K1/111 , G01R31/2818 , H05K1/0268 , H05K3/3452 , H05K2201/10674 , Y10T29/49004 , Y10T29/49124 , Y10T29/4913
摘要： Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (μm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.
摘要翻译：一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。在一些实施方案中，多个迹线具有100微米（μm）或更小的间距。在一些实施方式中，衬底是封装衬底。在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。在一些实施方式中，接合部件是焊球之一。

5. 发明授权

US09159670B2 Ultra fine pitch and spacing interconnects for substrate 有权
标题翻译：用于衬底的超细间距和间距互连
公开(公告)号：US09159670B2
公开(公告)日：2015-10-13
申请号：US14318490
申请日：2014-06-27
申请人： QUALCOMM Incorporated
发明人： Chin-Kwan Kim , Rajneesh Kumar , Omar James Bchir
IPC分类号： H01L21/4763 , H01L23/52 , H01L29/40 , H01L23/528 , H01L21/768 , H01L23/00 , H01L23/498
CPC分类号： H01L23/528 , H01L21/768 , H01L23/498 , H01L23/49827 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/14133 , H01L2224/16237 , H01L2224/16238 , H01L2224/17051 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H01L2924/3841 , H05K1/0296 , H05K1/111 , H05K3/4682 , H05K2201/0376 , H05K2201/094 , Y02P70/611 , H01L2924/00014 , H01L2924/014
摘要： Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.
摘要翻译：一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。第一介电层包括第一和第二表面。第一互连嵌入在第一电介质层中。第一互连包括第一侧和第二侧。第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

6. 发明申请

US20140322868A1 BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE 审中-公开
标题翻译： BARRIER LAYER ON BUMP和非易挥发涂层
公开(公告)号：US20140322868A1
公开(公告)日：2014-10-30
申请号：US14328618
申请日：2014-07-10
申请人： QUALCOMM Incorporated
发明人： Omar James Bchir , Milind Pravin Shah , Houssam Wafic Jomaa , Manuel Aldrete , Chin-Kwan Kim
IPC分类号： H01L23/00 , H05K1/09
CPC分类号： H01L24/06 , H01L21/563 , H01L23/49866 , H01L23/49894 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/10175 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81447 , H01L2224/81815 , H01L2224/83192 , H05K1/092 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.
摘要翻译：一些实施方案提供了一种半导体器件，其包括管芯，耦合到管芯的凹凸金属化（UBM）结构和阻挡层。 UBM结构具有第一氧化物性质。阻挡层具有比UBM结构的第一氧化物性质更能抵抗从焊剂材料中去除氧化物的第二氧化物性质。阻挡层包括顶部，底部和侧部。顶部连接到UBM结构，并且侧部被基本氧化。

7. 发明授权

US08772951B1 Ultra fine pitch and spacing interconnects for substrate 有权
标题翻译：用于衬底的超细间距和间距互连
公开(公告)号：US08772951B1
公开(公告)日：2014-07-08
申请号：US14014192
申请日：2013-08-29
申请人： QUALCOMM Incorporated
发明人： Chin-Kwan Kim , Rajneesh Kumar , Omar James Bchir
IPC分类号： H01L21/4763 , H01L29/40
CPC分类号： H01L23/498 , H01L21/4857 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/11 , H01L2224/14133 , H01L2224/16237 , H01L2224/16238 , H01L2224/17051 , H01L2224/81191 , H01L2224/81385 , H01L2224/81801 , H05K1/0296 , H05K1/111 , H05K3/4682 , H05K2201/0376 , H05K2201/09227
摘要： Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.
摘要翻译：一些新颖的特征涉及包括第一介电层，嵌入在第一介电层的第一表面中的第一互连以及在第一介电层的第一表面上的第二互连的衬底。第一互连件与第一介电层的第一表面偏移。第一互连件朝向第一介电层的内部部分偏移。在一些实施方案中，衬底还包括嵌入在第一介电层的第一表面中的第三互连和在第一介电层的第一表面上的第四互连。第一互连和第二互连是相邻的互连。在一些实施方案中，衬底还包括在第一介电层的第一表面上的第一焊盘。第一焊盘耦合到第一互连。

8. 发明授权

US09642259B2 Embedded bridge structure in a substrate 有权
公开(公告)号：US09642259B2
公开(公告)日：2017-05-02
申请号：US14067677
申请日：2013-10-30
申请人： QUALCOMM Incorporated
发明人： Chin-Kwan Kim , Omar James Bchir , Dong Wook Kim , Hong Bok We
IPC分类号： H05K7/10 , H05K7/12 , H05K1/18 , H05K1/11 , H01L23/538 , H01L25/065 , H01L23/00
CPC分类号： H05K1/18 , H01L23/5383 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/15192 , H01L2924/15313 , H05K1/11 , H01L2924/014
摘要： Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

9. 发明申请

US20150296616A1 PACKAGE SUBSTRATE COMPRISING SURFACE INTERCONNECT AND CAVITY COMPRISING ELECTROLESS FILL 有权
标题翻译：包含表面互连和包含电镀膜的孔的包装基底
公开(公告)号：US20150296616A1
公开(公告)日：2015-10-15
申请号：US14251486
申请日：2014-04-11
申请人： QUALCOMM Incorporated
发明人： Houssam Wafic Jomaa , Omar James Bchir , Chin-Kwan Kim
IPC分类号： H05K1/11 , H05K3/42 , H05K1/02
CPC分类号： H05K1/112 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2924/15311 , H05K1/0298 , H05K3/422 , H05K3/425 , H05K3/429 , H05K2201/0344 , H05K2201/09036 , H05K2201/10378
摘要： Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.
摘要翻译：一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。第一电介质层包括第一表面和第二表面。第一互连在衬底层的第一表面上。第一空腔穿过第一介电层的第一表面。第一无电金属层至少部分地形成在第一腔中。第一无电金属层限定嵌入在第一介电层中的第二互连。在一些实施方案中，衬底还包括芯层。芯层包括第一表面和第二表面。芯层的第一表面耦合到第一介电层的第二表面。在一些实施方案中，衬底还包括第二介电层。

10. 发明申请

US20150221528A9 PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC) 审中-公开
标题翻译：通过使用背面模具配置（BSMC）提高包装的温度和连接可靠性的过程
公开(公告)号：US20150221528A9
公开(公告)日：2015-08-06
申请号：US14255349
申请日：2014-04-17
申请人： QUALCOMM INCORPORATED
发明人： Omar James Bchir , Milind Pravin Shah , Sashidhar Movva
IPC分类号： H01L21/56 , H01L23/00
CPC分类号： H01L21/563 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81193 , H01L2224/92125 , H01L2924/01057 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.
摘要翻译：用于制造封装集成电路的背面模具配置（BSMC）工艺包括将模具化合物施加到与附接模具相对的封装基板的一侧。将模具化合物沉积在电介质（例如光致抗蚀剂）上。在将模具连接到包装基板上以暴露包装基板的接触垫之后，模制化合物和电介质被图案化。在模制化合物和电介质图案化之后，封装连接通过模具化合物和电介质耦合到接触垫。围绕包装连接的模具化合物减少处理期间包装基材的翘曲。此外，在连接芯片之后对电介质进行图案化提高了封装连接的可靠性。

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