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1. 发明授权

US11631450B2 Partial refresh technique to save memory refresh power 有权
公开(公告)号：US11631450B2
公开(公告)日：2023-04-18
申请号：US17377799
申请日：2021-07-16
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , Yanru Li , Michael Hawjing Lo , Dexter Tamio Chun
IPC分类号： G11C11/406 , G11C7/10 , G11C8/12
摘要： In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

2. 发明授权

US11372717B2 Memory with system ECC 有权
公开(公告)号：US11372717B2
公开(公告)日：2022-06-28
申请号：US16944110
申请日：2020-07-30
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , Michael Hawjing Lo , Dexter Tamio Chun , Xavier Loic Leloup , Laurent Rene Moll
IPC分类号： G06F11/10 , G06F3/06
摘要： Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

3. 发明授权

US10852809B2 Power saving techniques for memory systems by consolidating data in data lanes of a memory bus 有权
公开(公告)号：US10852809B2
公开(公告)日：2020-12-01
申请号：US16268634
申请日：2019-02-06
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , Dexter Tamio Chun , Michael Hawjing Lo
IPC分类号： G06F12/06 , G06F13/16 , G11C7/10 , G06F1/3234 , G06F1/3225 , G06F13/42
摘要： Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

4. 发明授权

US10394724B2 Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns 有权
公开(公告)号：US10394724B2
公开(公告)日：2019-08-27
申请号：US15243435
申请日：2016-08-22
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , Dexter Chun , Haw-Jing Lo
IPC分类号： G06F13/00 , G06F13/16
摘要： Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

5. 发明授权

US10331517B2 Link error correction in memory system 有权
公开(公告)号：US10331517B2
公开(公告)日：2019-06-25
申请号：US15643455
申请日：2017-07-06
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh
IPC分类号： G06F3/06 , H03M13/31 , G06F11/10
摘要： Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.

6. 发明授权

US10061645B2 Memory array and link error correction in a low power memory sub-system 有权
公开(公告)号：US10061645B2
公开(公告)日：2018-08-28
申请号：US14859063
申请日：2015-09-18
申请人： QUALCOMM Incorporated
发明人： Jungwon Suh , David Ian West
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/52
摘要： A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

7. 发明授权

US09911485B2 Method and apparatus for refreshing a memory cell 有权
公开(公告)号：US09911485B2
公开(公告)日：2018-03-06
申请号：US14244173
申请日：2014-04-03
申请人： QUALCOMM Incorporated
发明人： Deepti Vijayalakshmi Sriramagiri , Jung Pill Kim , Jungwon Suh , Xiangyu Dong
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40626 , G11C2211/406
摘要： A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

8. 发明授权

US09299457B2 Kernel masking of DRAM defects 有权
标题翻译： DRAM缺陷的内核屏蔽
公开(公告)号：US09299457B2
公开(公告)日：2016-03-29
申请号：US14187279
申请日：2014-02-23
申请人： QUALCOMM INCORPORATED
发明人： Dexter T. Chun , Yanru Li , Xiangyu Dong , Jungwon Suh , Jung Pill Kim , Deepti Vijayalakshmi Sriramagiri
IPC分类号： G11C29/00 , G11C29/44 , G06F11/10 , G06F11/20 , G06F12/02
CPC分类号： G11C29/44 , G06F11/1048 , G06F11/1076 , G06F11/2053 , G06F12/0246 , G06F2212/7209 , G11C2029/4402
摘要： Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.
摘要翻译：公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。

9. 发明授权

US09274888B2 Method and apparatus for multiple-bit DRAM error recovery 有权
标题翻译：用于多位DRAM错误恢复的方法和装置
公开(公告)号：US09274888B2
公开(公告)日：2016-03-01
申请号：US14081645
申请日：2013-11-15
申请人： QUALCOMM Incorporated
发明人： Dexter Tamio Chun , Jung Pill Kim , Hyunsuk Shin , Jungwon Suh
IPC分类号： G11C29/00 , G06F11/10 , G06F11/14
CPC分类号： G06F11/1072 , G06F11/1048 , G06F11/14 , G11C29/765
摘要： A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.
摘要翻译：当读取页面时，用于替换存储在系统存储器中的页面的系统产生多位错误。在读取检测到多位错误的系统存储器中的页面时，闪存中的备份数据被加载到系统存储器中的冗余页面中，并且配置重新映射器，以便将来对页面的访问被重定向到冗余页面。

10. 发明授权

US09224452B2 Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems 有权
标题翻译：异构存储器系统以及用于在基于处理器的系统中支持异构存储器访问请求的相关方法和计算机可读介质
公开(公告)号：US09224452B2
公开(公告)日：2015-12-29
申请号：US13743400
申请日：2013-01-17
申请人： QUALCOMM Incorporated
发明人： Xiangyu Dong , Jungwon Suh
IPC分类号： G06F13/16 , G06F12/08 , G11C11/406
CPC分类号： G11C11/40603 , G06F12/08 , G06F13/1694 , Y02D10/14
摘要： Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.
摘要翻译：公开了用于在基于处理器的系统中支持异构存储器访问请求的异构存储器系统以及相关方法和计算机可读介质。异构存储器系统由可以针对给定存储器访问请求访问的多个均匀存储器组成。每个均匀存储器具有特定的功率和性能特性。在这方面，存储器访问请求可以有利地基于存储器访问请求以及功率和/或性能考虑路由到异构存储器系统中的同构存储器之一。作为非限制性示例，异类存储器访问请求策略可以基于诸如读/写类型，页面命中的频率和存储器流量的关键操作参数动态地预定义或确定。以这种方式，存储器访问请求时间可以被优化以被减少，而不需要进行与仅具有可用于存储的一个存储器类型相关联的权衡。

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