专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11935606B2 Memory with scan chain testing of column redundancy logic and multiplexing 有权
公开(公告)号：US11935606B2
公开(公告)日：2024-03-19
申请号：US17364738
申请日：2021-06-30
申请人： QUALCOMM Incorporated
发明人： Rahul Sahu , Sharad Kumar Gupta , Jung Pill Kim , Chulmin Jung , Jais Abraham
IPC分类号： G11C29/10 , G11C7/06 , G11C7/10
CPC分类号： G11C29/10 , G11C7/06 , G11C7/106 , G11C7/1096
摘要： A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

2. 发明授权

US10263645B2 Error correction and decoding 有权
公开(公告)号：US10263645B2
公开(公告)日：2019-04-16
申请号：US15716451
申请日：2017-09-26
申请人： QUALCOMM Incorporated
发明人： Seong-Ook Jung , Sara Choi , Byung Kyu Song , Taehui Na , Jisu Kim , Jung Pill Kim , Sungryul Kim , Taehyun Kim , Seung Hyuk Kang
IPC分类号： H03M13/00 , G06F11/10 , H03M13/15
摘要： In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

3. 发明授权

US10185515B2 Unified memory controller for heterogeneous memory on a multi-chip package 有权
公开(公告)号：US10185515B2
公开(公告)日：2019-01-22
申请号：US14016717
申请日：2013-09-03
申请人： QUALCOMM Incorporated
发明人： Hyunsuk Shin , Jung Pill Kim , Dexter Tamio Chun , Jungwon Suh
IPC分类号： G06F3/06 , G06F13/16
摘要： An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

4. 发明授权

US09666259B1 Dual mode sensing scheme 有权
公开(公告)号：US09666259B1
公开(公告)日：2017-05-30
申请号：US15097166
申请日：2016-04-12
申请人： QUALCOMM Incorporated , Industry-Academic Cooperation Foundation, Yonsei University
发明人： Seong-Ook Jung , Taehui Na , Byung Kyu Song , Jung Pill Kim , Seung Hyuk Kang
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/065 , G11C11/1675
摘要： A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.

5. 发明授权

US09612908B2 Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods 有权
公开(公告)号：US09612908B2
公开(公告)日：2017-04-04
申请号：US14627268
申请日：2015-02-20
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Sungryul Kim , Jung Pill Kim
IPC分类号： G06F11/00 , G06F11/14 , G06F12/02 , G06F11/10
CPC分类号： G06F11/1402 , G06F11/106 , G06F12/023 , G06F12/0238 , G06F2201/805 , G06F2212/7205 , Y02D10/13
摘要： Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

6. 发明授权

US09583170B2 Adjusting resistive memory write driver strength based on a mimic resistive memory write operation 有权
标题翻译：基于模拟电阻式存储器写入操作调整电阻式存储器写入驱动器强度
公开(公告)号：US09583170B2
公开(公告)日：2017-02-28
申请号：US14620487
申请日：2015-02-12
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Jung Pill Kim , Sungryul Kim
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00
CPC分类号： G11C11/1675 , G11C11/1677 , G11C2013/0078
摘要： Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.
摘要翻译：公开了基于模拟电阻式存储器写入操作来调节电阻性存储器写入驱动器强度的方面。一方面，提供写入驱动器调整电路以将由写入驱动器提供的写入电流调整到用于写入操作的电阻性存储器。写驱动器调整电路包括模拟写驱动器，其配置为提供模拟写入电流，模拟写入电流提供给电阻存储器。模拟写入电流被施加到模拟电阻性存储器，其包含模拟电阻性存储器的电阻分布的模拟电阻存储器元件。当应用模拟写入电流时，在模拟电阻存储器元件之间产生模拟电压。写入驱动器调整电路被配置为基于模拟电压来调整写入电流，使得写入电流对于写入操作是足够的，但是足够低以减少击穿。

7. 发明授权

US09502088B2 Constant sensing current for reading resistive memory 有权
标题翻译：用于读取电阻性存储器的恒定感应电流
公开(公告)号：US09502088B2
公开(公告)日：2016-11-22
申请号：US14499155
申请日：2014-09-27
申请人： QUALCOMM Incorporated
发明人： Seong-Ook Jung , Sara Choi , Jisu Kim , Taehui Na , Jung Pill Kim , Seung Hyuk Kang
IPC分类号： G11C11/16 , G11C7/14 , G11C7/06 , G11C7/08 , G11C13/00
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/08 , G11C7/14 , G11C13/004 , G11C2013/0045 , G11C2013/0054
摘要： Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.
摘要翻译：系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

8. 发明授权

US09472261B1 Systems and methods to refresh DRAM based on temperature and based on calibration data 有权
标题翻译：基于温度和基于校准数据刷新DRAM的系统和方法
公开(公告)号：US09472261B1
公开(公告)日：2016-10-18
申请号：US14690204
申请日：2015-04-17
申请人： QUALCOMM Incorporated
发明人： Dexter Tamio Chun , Jung Pill Kim , Yanru Li
IPC分类号： G11C5/00 , G11C7/00 , G11C29/00 , G11C7/04 , G11C11/406 , G11C11/4096 , G11C29/42 , G11C29/36
CPC分类号： G11C11/40626 , G11C7/1006 , G11C11/4076 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/36 , G11C29/42 , G11C29/50016 , G11C2207/2245 , G11C2211/4062
摘要： A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.
摘要翻译：公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

9. 发明授权

US09455031B2 System and method for MRAM having controlled averagable and isolatable voltage reference 有权
标题翻译： MRAM的系统和方法具有可控的可分离和可分离的电压参考
公开(公告)号：US09455031B2
公开(公告)日：2016-09-27
申请号：US14161850
申请日：2014-01-23
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Taehyun Kim
IPC分类号： G11C11/00 , G11C13/00 , G11C5/06 , G11C7/08 , G11C29/02
CPC分类号： G11C13/004 , G11C5/063 , G11C7/08 , G11C11/1673 , G11C13/0038 , G11C13/0069 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A memory has a plurality of non-volatile resistive (NVR) memory arrays, each with an associated reference voltage generating circuit coupled by a reference circuit coupling link to a reference line, the reference coupled to a sense amplifier for that NVR memory array. Reference line coupling links couple the reference lines of different NVR memory arrays. Optionally, different ones of the reference coupling links are removed or opened, obtaining respective different average and isolated reference voltages on the different reference lines. Optionally, different ones of the reference circuit coupling links are removed or opened, obtaining respective different averaged voltages on the reference lines, and uncoupling and isolating different reference circuits.
摘要翻译：存储器具有多个非易失性电阻（NVR）存储器阵列，每个存储阵列具有通过参考电路耦合到参考线的参考电压产生电路，该参考电压产生电路耦合到用于该NVR存储器阵列的读出放大器。参考线耦合链路耦合不同NVR存储器阵列的参考线。可选地，不同的参考耦合链路被去除或打开，在不同的参考线上获得各自不同的平均和隔离参考电压。可选地，去除或打开不同的参考电路耦合链路，在参考线上获得各自不同的平均电压，以及解耦和隔离不同的参考电路。

10. 发明申请

US20160267959A1 WRITE DRIVER CIRCUITS FOR RESISTIVE RANDOM ACCESS MEMORY (RAM) ARRAYS 有权
标题翻译：用于电阻随机存取存储器（RAM）阵列的写驱动电路
公开(公告)号：US20160267959A1
公开(公告)日：2016-09-15
申请号：US14644631
申请日：2015-03-11
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Sungryul Kim , Taehyun Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.
摘要翻译：在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式