专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10523253B2 Glass substrate including passive-on-glass device and semiconductor die 有权
公开(公告)号：US10523253B2
公开(公告)日：2019-12-31
申请号：US16029432
申请日：2018-07-06
申请人： QUALCOMM Incorporated
发明人： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
IPC分类号： H04B1/16 , H01L21/48 , H01L23/522 , H01L23/64 , H01L23/00 , H04B1/00 , H05K1/16 , H05K1/18 , H05K3/46 , H01L23/498 , H01L23/66 , H01L27/01 , H01L49/02 , H01F17/00
摘要： In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

2. 发明授权

US10044390B2 Glass substrate including passive-on-glass device and semiconductor die 有权
公开(公告)号：US10044390B2
公开(公告)日：2018-08-07
申请号：US15216615
申请日：2016-07-21
申请人： QUALCOMM Incorporated
发明人： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
IPC分类号： H01L23/28 , H03H7/46 , H04B1/401 , H05K1/18 , H04B1/16 , H01L27/01 , H01L49/02 , H01L23/498 , H01L23/66 , H01L21/48
摘要： In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

3. 发明授权

US09935166B2 Capacitor with a dielectric between a via and a plate of the capacitor 有权
公开(公告)号：US09935166B2
公开(公告)日：2018-04-03
申请号：US13833632
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Je-Hsiung Lan , Chengjie Zuo , Changhan Yun , David F. Berdy , Daeik D. Kim , Robert P. Mikulka , Mario Francisco Velez , Jonghae Kim
IPC分类号： H05K1/16 , H01L49/02 , G06F17/50 , H01L23/498 , H01L27/01 , H01L23/15 , H01L27/12
CPC分类号： H01L28/40 , G06F17/5068 , H01L23/15 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L27/016 , H01L27/12 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

4. 发明申请

US20180026666A1 GLASS SUBSTRATE INCLUDING PASSIVE-ON-GLASS DEVICE AND SEMICONDUCTOR DIE 审中-公开
公开(公告)号：US20180026666A1
公开(公告)日：2018-01-25
申请号：US15216615
申请日：2016-07-21
申请人： QUALCOMM Incorporated
发明人： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
IPC分类号： H04B1/16 , H01L21/48 , H01L23/498 , H01L23/66 , H01L27/01 , H01L49/02
CPC分类号： H04B1/1638 , H01F17/0013 , H01L21/4853 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/5223 , H01L23/64 , H01L23/66 , H01L24/19 , H01L24/20 , H01L27/01 , H01L28/10 , H01L28/40 , H01L2223/6616 , H01L2223/6672 , H01L2223/6677 , H01L2223/6688 , H01L2224/04105 , H01L2224/24195 , H01L2924/10253 , H01L2924/13091 , H01L2924/1421 , H01L2924/15153 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H04B1/006 , H05K1/165 , H05K1/185 , H05K3/4605 , H05K2201/09536 , H05K2201/097
摘要： In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

5. 发明授权

US09634640B2 Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods 有权
公开(公告)号：US09634640B2
公开(公告)日：2017-04-25
申请号：US13887568
申请日：2013-05-06
申请人： QUALCOMM Incorporated
发明人： Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
IPC分类号： H03H7/46
CPC分类号： H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
摘要： Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

6. 发明授权

US09431510B2 Metal-semiconductor wafer bonding for high-Q devices 有权
标题翻译：用于高Q器件的金属半导体晶片接合
公开(公告)号：US09431510B2
公开(公告)日：2016-08-30
申请号：US14554718
申请日：2014-11-26
申请人： QUALCOMM Incorporated
发明人： Changhan Yun , Chengjie Zuo , Chi Shun Lo , Jonghae Kim , Mario F. Velez
IPC分类号： H01L21/20 , H01L29/66 , H01G4/33 , H01L49/02 , H01G4/12
CPC分类号： H01L29/66174 , H01G4/1272 , H01G4/33 , H01L28/40 , H01L28/75
摘要： Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
摘要翻译：提供了用于高Q装置的金属半导体晶片接合的方法和装置。示例性电容器包括形成在玻璃基板，第二板和介电层上的第一板。在第一板和玻璃基板之间不使用有机粘合剂，并且电介质层可以是本征半导体。重掺杂的非本征半导体层接触电介质层。电介质和非本征半导体层夹在第一和第二板之间。在第一板和电介质层之间形成金属间层。金属间化合物层被热压接合到第一板和电介质层。电容器可以作为高Q电容器和/或变容二极管耦合在电路中，并且可以与移动设备集成。

7. 发明申请

US20140252645A1 THERMAL DESIGN AND ELECTRICAL ROUTING FOR MULTIPLE STACKED PACKAGES USING THROUGH VIA INSERT (TVI) 有权
标题翻译：使用通过插入（TVI）的多个堆叠包的热设计和电气路由
公开(公告)号：US20140252645A1
公开(公告)日：2014-09-11
申请号：US13787476
申请日：2013-03-06
申请人： QUALCOMM INCORPORATED
发明人： Dong Wook Kim , Victor A. Chiriac , Kyu-Pyung Hwang , Changhan Yun , Young K. Song
IPC分类号： H01L23/34
CPC分类号： H01L23/34 , H01L23/367 , H01L23/3677 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.
摘要翻译：一些实施方案提供半导体封装结构，其包括封装衬底，第一封装，耦合到第一封装的插入器和第一组通孔插入件（TVI）。第一组TVI耦合到插入器和封装衬底。第一组TVI配置为提供第一包装散热。在一些实施方案中，半导体封装结构还包括耦合到插入件的散热器。散热器被配置为从第一包装散发热量。在一些实施方式中，第一组TVI被进一步配置成在第一封装和封装衬底之间提供电路径。在一些实施方案中，第一封装通过插入器和第一组TVI电耦合到封装衬底。在一些实施方案中，第一组TVI包括电介质层和金属层。

8. 发明授权

US10325855B2 Backside drill embedded die substrate 有权
公开(公告)号：US10325855B2
公开(公告)日：2019-06-18
申请号：US15074750
申请日：2016-03-18
申请人： QUALCOMM Incorporated
发明人： Daeik Kim , Jie Fu , Changhan Yun , Chin-Kwan Kim , Manuel Aldrete , Chengjie Zuo , Mario Velez , Jonghae Kim
IPC分类号： H01L23/538 , H01L21/48 , H01L21/768 , H01L23/48 , H01L23/498 , H01L23/00
摘要： A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

9. 发明授权

US10039188B2 Two-stage power delivery architecture 有权
公开(公告)号：US10039188B2
公开(公告)日：2018-07-31
申请号：US14811813
申请日：2015-07-28
申请人： QUALCOMM Incorporated
发明人： Changhan Yun , Francesco Carobolante , Chengjie Zuo , Jonghae Kim , Mario Francisco Velez , Lawrence D. Smith , Matthew M. Nowak
IPC分类号： H05K1/16 , H05K1/02 , H01L23/498 , H05K7/10 , H05K3/10 , H05K3/30 , H05K3/00
CPC分类号： H05K1/165 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/15788 , H01L2924/19105 , H05K1/0231 , H05K1/0243 , H05K1/0262 , H05K3/0091 , H05K3/10 , H05K3/30 , H05K7/1092 , Y10T29/4913 , Y10T29/49131 , Y10T29/49147 , Y10T29/49156
摘要： A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

10. 发明授权

US09331665B2 Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods 有权
公开(公告)号：US09331665B2
公开(公告)日：2016-05-03
申请号：US13887568
申请日：2013-05-06
申请人： QUALCOMM Incorporated
发明人： Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
IPC分类号： H03H7/46
摘要： Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式