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1. 发明授权

US07210008B2 Memory controller for padding and stripping data in response to read and write commands 有权
标题翻译：内存控制器，用于根据读写命令填充和解除数据
公开(公告)号：US07210008B2
公开(公告)日：2007-04-24
申请号：US10741298
申请日：2003-12-18
申请人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.
摘要翻译：存储器控制器，其包括到第一存储器的接口以及将存储器控制器耦合到至少一个处理器的总线的接口。控制器还包括电路，响应于通过总线从至少一个处理器接收的读取和写入命令，将数据移位由至少一些读取和写入命令所标识的量。

2. 发明授权

US07185153B2 Packet assembly 失效
标题翻译：数据包组装
公开(公告)号：US07185153B2
公开(公告)日：2007-02-27
申请号：US10742189
申请日：2003-12-18
申请人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： G06F12/00
CPC分类号： H04L69/166 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9052 , H04L67/02 , H04L69/16 , H04L69/329 , H04L2012/5652
摘要： In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.
摘要翻译：一般来说，在一个方面，本公开描述了一种在存储器中组装分组的方法。该方法包括读取分组到多个分组的分组的第一分段中的数据，并向存储器控制器发出命令，该命令使得存储器控制器将读取的数据的子集移位并写入耦合到存储器控制器的存储器。该方法还包括将剩余的读取数据保存为第一残余，检索包含在分组的第二段中的数据，以及将所检索的数据和第一残差的至少一部分写入存储器。

3. 发明申请

US20050135353A1 Packet assembly 失效
标题翻译：数据包组装
公开(公告)号：US20050135353A1
公开(公告)日：2005-06-23
申请号：US10742189
申请日：2003-12-18
申请人： Prashant Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： H04L12/28 , H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L69/166 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9052 , H04L67/02 , H04L69/16 , H04L69/329 , H04L2012/5652
摘要： In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.
摘要翻译：通常，在一个方面，本公开描述了一种在存储器中组装分组的方法。该方法包括读取分组到多个分组的分组的第一分段中的数据，并向存储器控制器发出命令，该命令使得存储器控制器将读取的数据的子集移位并写入耦合到存储器控制器的存储器。该方法还包括将剩余的读取数据保存为第一残余，检索包含在分组的第二段中的数据，以及将所检索的数据和第一残差的至少一部分写入存储器。

4. 发明申请

US20050135367A1 Memory controller 有权
标题翻译：内存控制器
公开(公告)号：US20050135367A1
公开(公告)日：2005-06-23
申请号：US10741298
申请日：2003-12-18
申请人： Prashant Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： H04L12/28
CPC分类号： G06F13/1678
摘要： In general, in one aspect, the disclosure describes a memory controller. The controller includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.
摘要翻译：通常，在一个方面，本公开描述了一种存储器控制器。控制器包括到第一存储器的接口以及将存储器控制器耦合到至少一个处理器的总线的接口。控制器还包括电路，响应于通过总线从至少一个处理器接收的读取和写入命令，将数据移位由至少一些读取和写入命令所标识的量。

5. 发明授权

US07437510B2 Instruction-assisted cache management for efficient use of cache and memory 有权
标题翻译：指令辅助缓存管理，用于缓存和内存的高效使用
公开(公告)号：US07437510B2
公开(公告)日：2008-10-14
申请号：US11241538
申请日：2005-09-30
申请人： Mark Rosenbluth , Sridhar Lakshmanamurthy
发明人： Mark Rosenbluth , Sridhar Lakshmanamurthy
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0888 , G06F12/126
摘要： Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.
摘要翻译：指令辅助缓存管理，用于缓存和内存的高效使用。添加提示（例如修饰符）来读取和写入存储器访问指令以识别用于时间数据的存储器访问。鉴于这样的提示，实现了使缓存和存储器访问最小化的替代高速缓存策略和分配策略。在一个策略下，写高速缓存未命中可能导致将数据写入部分高速缓存行而没有存储器读/写周期来填充该行的其余部分。在另一种策略下，读高速缓存未命中可能导致从存储器的读取，而无需将读取的数据分配或写入高速缓存行。还公开了一种高速缓存行软锁定机制，其中高速缓存行可以被可选地软锁定以指示将这些高速缓存行保持在非锁定行上的偏好。

6. 发明申请

US20070079073A1 Instruction-assisted cache management for efficient use of cache and memory 有权
标题翻译：指令辅助缓存管理，用于缓存和内存的高效使用
公开(公告)号：US20070079073A1
公开(公告)日：2007-04-05
申请号：US11241538
申请日：2005-09-30
申请人： Mark Rosenbluth , Sridhar Lakshmanamurthy
发明人： Mark Rosenbluth , Sridhar Lakshmanamurthy
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0804 , G06F12/0888 , G06F12/126
摘要： Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.
摘要翻译：指令辅助缓存管理，用于缓存和内存的高效使用。添加提示（例如修饰符）来读取和写入存储器访问指令以识别用于时间数据的存储器访问。鉴于这样的提示，实现了使缓存和存储器访问最小化的替代高速缓存策略和分配策略。在一个策略下，写高速缓存未命中可能导致将数据写入部分高速缓存行而没有存储器读/写周期来填充该行的其余部分。在另一种策略下，读高速缓存未命中可能导致从存储器的读取，而无需将读取的数据分配或写入高速缓存行。还公开了一种高速缓存行软锁定机制，其中高速缓存行可以被可选地软锁定以指示将这些高速缓存行保持在非锁定行上的偏好。

7. 发明申请

US20060112206A1 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US20060112206A1
公开(公告)日：2006-05-25
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
IPC分类号： G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

8. 发明申请

US20060002412A1 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US20060002412A1
公开(公告)日：2006-01-05
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
IPC分类号： H04L12/28
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

9. 发明申请

US20060221980A1 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
公开(公告)号：US20060221980A1
公开(公告)日：2006-10-05
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： H04L12/56 , H04L12/28 , H04L12/66
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.

10. 发明授权

US07360031B2 Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces 有权
标题翻译：使I / O代理能够在共享的，一致的存储器空间中执行原子操作的方法和装置
公开(公告)号：US07360031B2
公开(公告)日：2008-04-15
申请号：US11171155
申请日：2005-06-29
申请人： Sridhar Lakshmanamurthy , Mason B. Cabot , Sameer Nanavati , Mark Rosenbluth
发明人： Sridhar Lakshmanamurthy , Mason B. Cabot , Sameer Nanavati , Mark Rosenbluth
IPC分类号： G06F12/02
CPC分类号： G06F13/1663 , G06F12/0835
摘要： Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space. If the cache snoop identifies a modified cache line, a copy of that cache line is returned to the I/O agent; otherwise, the copy of the data retrieved from the shared memory space is returned.
摘要翻译：使I / O代理能够在共享的，一致的存储器空间中执行原子操作的方法和装置。该装置包括仲裁单元，主机接口单元和存储器接口单元。仲裁单元向一个或多个发出原子事务的I / O代理提供接口以访问和/或修改存储在经由存储器接口单元访问的共享存储器空间中的数据。主机接口单元与一个或多个处理器可以耦合到的前端总线（FSB）相连接。为了响应由I / O代理发出的原子事务，事务被分成两个相互依赖的进程。在一个过程中，入站写入事务被注入到主机接口单元中，然后驱动FSB使处理器执行缓存窥探。同时，入站读取事务被注入到存储器接口单元中，该单元从共享存储器空间检索数据的副本。如果缓存侦听器识别修改后的高速缓存行，则将该高速缓存行的副本返回给I / O代理; 否则，返回从共享存储空间检索的数据的副本。

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