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1. 发明申请

US20060002412A1 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US20060002412A1
公开(公告)日：2006-01-05
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark Rosenbluth
IPC分类号： H04L12/28
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

2. 发明申请

US20060221980A1 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
公开(公告)号：US20060221980A1
公开(公告)日：2006-10-05
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： H04L12/56 , H04L12/28 , H04L12/66
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.

3. 发明申请

US20060047873A1 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US20060047873A1
公开(公告)日：2006-03-02
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/14
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

4. 发明授权

US07200699B2 Scalable, two-stage round robin arbiter with re-circulation and bounded latency 有权
标题翻译：可扩展的两阶段循环仲裁器具有重新循环和有限延迟
公开(公告)号：US07200699B2
公开(公告)日：2007-04-03
申请号：US10933621
申请日：2004-09-02
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin Vaz , Alok Mathur
IPC分类号： G06F13/368
CPC分类号： G06F13/4022 , G06F13/362
摘要： A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between command requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first stage command requests. One embodiment of the arbitration scheme employs re-circulation of second stage losers. Another embodiment employs re-prioritization of second stage losers.
摘要翻译：可扩展的两阶段循环仲裁器，具有重新循环和有限延迟，可用于多线程多处理器件。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的命令请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段命令请求之间进行仲裁。仲裁方案的一个实施例采用第二阶段输家的再循环。另一个实施例使用第二阶段输家的重新排序。

5. 发明授权

US07412551B2 Methods and apparatus for supporting programmable burst management schemes on pipelined buses 有权
标题翻译：在流水线总线上支持可编程突发管理方案的方法和装置
公开(公告)号：US07412551B2
公开(公告)日：2008-08-12
申请号：US10882375
申请日：2004-06-30
申请人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
发明人： Bijoy Bose , Irwin Vaz , Sridhar Lakshmanamurthy , Mark B. Rosenbluth
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , H04L49/101 , H04L49/102 , H04L49/15 , H04L49/45
摘要： Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes one or more shared resource targets. A scalable chassis infrastructure is used to interconnect the targets with the clusters using a crossbar interconnect configuration including pipelined command, and data buses. The interconnect includes sub-group multiplexers for each sub-group and sub-group selection multiplexers coupled to each cluster. A two-stage arbiter, operatively coupled to the targets, sub-group multiplexers, and sub-group selection multiplexers, is employed to arbitrate transaction requests issued from the masters to the targets and manage transactions. The two-stage arbiter includes a provision for supporting programmable burst management, wherein selected sub-groups can be tuned for handling short or long burst traffic.
摘要翻译：在流水线总线上支持可编程突发管理方案的方法和装置。该装置包括配置在多个群集中的多个总线主站（主站）和多个目标子组。每个目标子组包括一个或多个共享资源目标。可扩展的机箱基础架构用于使用包括流水线命令和数据总线的交叉连接配置将目标与群集互连。互连包括用于每个子组的子组多路复用器和耦合到每个集群的子组选择多路复用器。使用可操作地耦合到目标的两级仲裁器，子组多路复用器和子组选择多路复用器来仲裁从主人发送到目标的事务请求并管理事务。两级仲裁器包括用于支持可编程突发管理的规定，其中可以调整所选择的子组以处理短或长突发流量。

6. 发明申请

US20060112206A1 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US20060112206A1
公开(公告)日：2006-05-25
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark Rosenbluth , Matthew Adiletta , Jeen-Yuan Miin , Bijoy Bose
IPC分类号： G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

7. 发明授权

US07707266B2 Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit 失效
标题翻译：可扩展的，高性能的全球互连方案，用于多线程，多处理系统级芯片网络处理器单元
公开(公告)号：US07707266B2
公开(公告)日：2010-04-27
申请号：US10997624
申请日：2004-11-23
申请人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
发明人： Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Matthew Adiletta , Jeen-Xuan Miin , Bijoy Bose
IPC分类号： G06F13/00 , G06F15/173 , G06F15/16
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
摘要翻译：用于多线程，多处理片上系统处理器单元的可扩展的高性能互连方案。实现该技术的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。在一个实施例中，机箱互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线路，用于目标的拉动数据总线写入和用于目标读取的推送数据总线。采用用于每个命令总线，拉数据总线和推数据总线的多路复用器电路来选择性地将给定集群连接到给定目标，以使命令和数据能够在给定集群和给定目标之间传递。

8. 发明授权

US07512729B2 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency 有权
标题翻译：具有可预测仲裁延迟的高效率两阶段旋转优先仲裁器的方法和装置
公开(公告)号：US07512729B2
公开(公告)日：2009-03-31
申请号：US11097067
申请日：2005-03-31
申请人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin J. Vaz , Suri Medapati , Edwin O'Yang
发明人： Bijoy Bose , Sridhar Lakshmanamurthy , Mark B. Rosenbluth , Irwin J. Vaz , Suri Medapati , Edwin O'Yang
IPC分类号： G06F13/00
CPC分类号： H04L49/101 , H04L49/254
摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.
摘要翻译：一种可扩展的两阶段旋转优先仲裁器，具有重新循环和有限延迟，可用于多线程多处理设备。实现两级仲裁器的装置包括配置在多个集群中的多个主机，多个目标以及可被控制以选择性地将给定主机连接到给定目标的机箱互连。底盘互连包括连接在多个群集之间的多组总线，并且多个目标形成横杆互连，包括对应于命令总线的总线线。采用两阶段仲裁方案仲裁访问命令总线。第一个仲裁阶段用于在给定群集中由主人发出的目标请求之间进行仲裁。第二仲裁阶段用于在获胜的第一阶段目标请求之间进行仲裁。仲裁方案的一个实施例在第一阶段采用旋转优先权仲裁方案。另一实施例在第二阶段采用互补旋转优先权仲裁方案。

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