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1. 发明授权

US07519823B1 Concealed, non-intrusive watermarks for configuration bitstreams 有权
标题翻译：隐藏的非侵入式水印用于配置比特流
公开(公告)号：US07519823B1
公开(公告)日：2009-04-14
申请号：US10917042
申请日：2004-08-12
申请人： Paul R. Schumacher , Robert D. Turney , Mark Paluszkiewicz , Prasanna Sundararajan , Brandon J. Blodget
发明人： Paul R. Schumacher , Robert D. Turney , Mark Paluszkiewicz , Prasanna Sundararajan , Brandon J. Blodget
IPC分类号： H04L9/00
CPC分类号： G06F21/76 , G06F21/16 , H04L9/0662 , H04L2209/12 , H04L2209/16 , H04L2209/608
摘要： Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.
摘要翻译：公开了用于在可编程逻辑器件（PLD）的配置比特流中嵌入标识符信息的各种方法。在各种实施例中，识别在实现设计时未使用的配置比特流中的比特。标识符信息被加密，并且使用伪随机函数来选择未使用位的子集。加密的标识符信息被放置在所选未使用的子集的子集中。解密是通过逆转加密方法来实现的。

2. 发明申请

US20100183081A1 GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING 有权
标题翻译：一般缓冲电路和带状信号的方法
公开(公告)号：US20100183081A1
公开(公告)日：2010-07-22
申请号：US12357369
申请日：2009-01-21
申请人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： H04B3/00
CPC分类号： G06F13/4072
摘要： Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.
摘要翻译：差分信号接口的电路和方法，用于将一对相反极性信号上的第一频率的差分信号耦合到具有用于以比第一频率低的第二频率接收，发射或收发带外信号的多吉比特收发器被披露。提供了端接网络，其将通用输入缓冲器耦合到一对相反极性信号中的相应极性信号，用于接收带外信号，其中相反极性信号被置于电压处，使得它们之间的差分电压低于阈值电压。提供了用于向通用缓冲器提供用于在差分信号接口上接收和发送带外信号的多个千兆位收发器的方法。当带外信令协议不知道时，接收带外信号。

3. 发明授权

US07948269B1 System and method for open drain/open collector structures in an integrated circuit 有权
标题翻译：集成电路中开漏/集电极结构的系统和方法
公开(公告)号：US07948269B1
公开(公告)日：2011-05-24
申请号：US12356267
申请日：2009-01-20
申请人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： H03K19/00 , H03K19/02
CPC分类号： H03K19/017545 , H03K19/017581
摘要： In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q1) that has a first terminal coupled to a bus line terminal, and a second driving device (Q2) that has a first terminal coupled to the bus line terminal. The first driving device (Q1) is configured to couple the bus line terminal to a reference voltage when activated by a first control signal, and the second driving device (Q2) is configured to couple the bus line terminal to a first supply voltage (Vcc) when the second driving device (Q2) is activated by a second control signal. The output driver also has a controller configured to activate the second control signal after the first control signal is deactivated. The second control signal remains active for a first fixed period of time.
摘要翻译：在一个实施例中，公开了一种输出驱动器。输出驱动器具有第一驱动装置（Q1），其具有耦合到总线端子的第一端子和具有耦合到总线端子的第一端子的第二驱动装置（Q2）。第一驱动装置（Q1）被配置为当由第一控制信号激活时将总线端子耦合到参考电压，并且第二驱动装置（Q2）被配置为将总线端子耦合到第一电源电压（Vcc ）当第二驱动装置（Q2）被第二控制信号激活时。输出驱动器还具有控制器，其被配置为在第一控制信号被去激活之后激活第二控制信号。第二控制信号在第一固定时间段内保持有效。

4. 发明授权

US07786762B2 Generic buffer circuits and methods for out of band signaling 有权
标题翻译：通用缓冲电路和带外信令的方法
公开(公告)号：US07786762B2
公开(公告)日：2010-08-31
申请号：US12357369
申请日：2009-01-21
申请人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： H03K19/0175
CPC分类号： G06F13/4072
摘要： Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.
摘要翻译：差分信号接口的电路和方法，用于将一对相反极性信号上的第一频率的差分信号耦合到具有用于以比第一频率低的第二频率接收，发射或收发带外信号的多吉比特收发器被披露。提供了端接网络，其将通用输入缓冲器耦合到一对相反极性信号中的相应极性信号，用于接收带外信号，其中相反极性信号被置于电压处，使得它们之间的差分电压低于阈值电压。提供了用于向通用缓冲器提供用于在差分信号接口上接收和发送带外信号的多个千兆位收发器的方法。当带外信令协议不知道时，接收带外信号。

5. 发明授权

US08352659B1 Segmentation and reassembly of a data value communicated via interrupt transactions 有权
标题翻译：通过中断事务传递的数据值的分段和重组
公开(公告)号：US08352659B1
公开(公告)日：2013-01-08
申请号：US12609338
申请日：2009-10-30
申请人： Henry E. Styles , Richard S. Ballantyne , Mark Paluszkiewicz , Ralph D. Wittig
发明人： Henry E. Styles , Richard S. Ballantyne , Mark Paluszkiewicz , Ralph D. Wittig
IPC分类号： G06F13/24 , G06F13/14
CPC分类号： G06F13/24
摘要： Approaches for communicating data from a source device to a target device. In one approach, a communicated data value is segmented into a plurality of data chunks at the source device. A sequence of interrupt transactions is transmitted from the source device to a system bus. The transmitting of each interrupt transaction in the sequence includes transmitting a target identifier on an address bus of the system bus, and the target identifier of each interrupt transaction in the sequence includes a respective one of the data chunks. The sequence of interrupt transactions from the system bus is received at the target device. The communicated data value is reassembled at the target device from the data chunks in the target identifier of the interrupt transactions in the sequence.
摘要翻译：将数据从源设备传送到目标设备的方法。在一种方法中，传送的数据值被分割成在源设备处的多个数据块。一系列中断事务从源设备发送到系统总线。序列中的每个中断事务的发送包括在系统总线的地址总线上发送目标标识符，并且序列中每个中断事务的目标标识符包括相应的一个数据块。在目标设备处接收来自系统总线的中断事务序列。所传送的数据值在目标设备中从序列中的中断事务的目标标识符中的数据块重新组合。

6. 发明授权

US07684278B1 Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit 有权
标题翻译：在集成电路中使用时分多路复用存储器来实现FIFO的方法和装置
公开(公告)号：US07684278B1
公开(公告)日：2010-03-23
申请号：US12198733
申请日：2008-08-26
申请人： Paul R. Schumacher , Mark Paluszkiewicz , Kornelis A. Vissers
发明人： Paul R. Schumacher , Mark Paluszkiewicz , Kornelis A. Vissers
IPC分类号： G11C8/00
CPC分类号： G06F5/16
摘要： Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.
摘要翻译：描述了使用集成电路中的时分复用存储器来实现先进先出（FIFO）存储器的方法和装置。提供嵌入在集成电路中的块随机存取存储器（BRAM）电路。 BRAM包括响应于相应的至少一个BRAM时钟信号的至少一个端口。 FIFO逻辑被配置为在具有多个接口的BRAM中实现多个FIFO。多路复用器逻辑被配置为响应于至少一个FIFO时钟信号，将FIFO逻辑的多个输出接口选择性地耦合到BRAM电路的至少一个端口。所述至少一个BRAM时钟信号中的每一个具有至少一个FIFO时钟信号中相应一个的频率的至少两倍。

7. 发明授权

US08296557B1 Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism 有权
标题翻译：为具有故障安全机制的可编程集成电路提供多种可选配置源
公开(公告)号：US08296557B1
公开(公告)日：2012-10-23
申请号：US12609174
申请日：2009-10-30
申请人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： G06F1/24 , G06F9/00
CPC分类号： G06F15/7871 , H03K19/1776 , H03K19/17768
摘要： Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circuit that accesses a data source external to the system over a communication link. A second configuration can be downloaded by the programmable IC from the data source. The second configuration can be stored within a random access memory within the system that is independent of the programmable IC. Responsive to a reconfiguration event, the programmable IC can be loaded with the second configuration from the random access memory.
摘要翻译：在包括可编程集成电路（IC）的系统中，一种方法可以包括将系统内的第一配置存储在独立于可编程IC的只读存储器中。被加载了第一配置的可编程IC包括通过通信链路访问系统外部的数据源的电路。可由可编程IC从数据源下载第二配置。第二配置可以存储在系统内的与可编程IC无关的随机存取存储器中。响应于重新配置事件，可编程IC可以从随机存取存储器加载第二配置。

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