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1. 发明授权

US09378003B1 Compiler directed cache coherence for many caches generated from high-level language source code 有权
标题翻译：针对高级语言源代码生成的许多缓存的编译器定向缓存一致性
公开(公告)号：US09378003B1
公开(公告)日：2016-06-28
申请号：US12508437
申请日：2009-07-23
申请人： Prasanna Sundararajan , Andrew R. Putnam , Jeffrey M. Mason
发明人： Prasanna Sundararajan , Andrew R. Putnam , Jeffrey M. Mason
IPC分类号： G06F9/45
CPC分类号： G06F8/4441 , G06F8/443 , G06F8/4442 , G06F8/452 , G06F8/454 , G06F8/456
摘要： Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.
摘要翻译：生成和操作电子系统的方法。高级语言（HLL）源代码被编译成等效的中间语言程序代码。编译确定用于存储由HLL源引用的数据的多个高速缓存。刷新指令插入中间语言程序。每个刷新指令引用一个缓存，并且在紧跟在最后写入该缓存的指令之后插入到中间语言程序中。中间语言程序被转换为指定多个高速缓存的硬件描述，用于处理高速缓存中的数据的电路，以及用于每个高速缓存的闪存接口，其响应于刷新而启动从高速缓存向主存储器写入数据信号。基于中间语言程序中的一个或多个刷新指令中的一个的布置来确定各个刷新信号的定时。

2. 发明授权

US08468510B1 Optimization of cache architecture generated from a high-level language description 有权
标题翻译：从高级语言描述生成的缓存架构的优化
公开(公告)号：US08468510B1
公开(公告)日：2013-06-18
申请号：US12508404
申请日：2009-07-23
申请人： Prasanna Sundararajan , Andrew R. Putnam , David W. Bennett
发明人： Prasanna Sundararajan , Andrew R. Putnam , David W. Bennett
IPC分类号： G06F9/45 , G06F13/00 , G06F13/28
CPC分类号： G06F17/505 , G06F17/5054
摘要： Approaches for generating a hardware specification from a high-level language (HLL) program. In one approach, a method determines separate accesses in the HLL program to multiple consecutively addressed data items. The HLL program is compiled into an intermediate language program to include one or more instructions that perform functions on the multiple consecutively addressed data items and one or more memory access instructions that reference the consecutively addressed data items. The method generates a hardware specification from the intermediate language program. The hardware specification includes a cache memory that caches the consecutively addressed data items and that accesses the consecutively addressed data items in response to a single access request. The specification further includes one or more hardware blocks that implement the functions of the instructions in the intermediate language program. At least one of hardware blocks has access to the multiple consecutively addressed data items in parallel.
摘要翻译：从高级语言（HLL）程序生成硬件规范的方法。在一种方法中，一种方法确定HLL程序中的多个连续寻址数据项的单独访问。 HLL程序被编译成中间语言程序，以包括对多个连续寻址的数据项执行功能的一个或多个指令以及引用连续寻址的数据项的一个或多个存储器访问指令。该方法从中间语言程序生成硬件规范。硬件规范包括高速缓冲存储器，其缓存连续寻址的数据项，并且响应于单个访问请求访问连续寻址的数据项。该规范还包括实现中间语言程序中的指令的功能的一个或多个硬件块。硬件块中的至少一个并行地访问多个连续寻址的数据项。

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