专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07456654B1 Method and apparatus for a programmable level translator 有权
标题翻译：用于可编程电平转换器的方法和装置
公开(公告)号：US07456654B1
公开(公告)日：2008-11-25
申请号：US11639995
申请日：2006-12-14
申请人： Prasad Rau , Venu M. Kondapalli , Jason R. Bergendahl , Qi Zhang
发明人： Prasad Rau , Venu M. Kondapalli , Jason R. Bergendahl , Qi Zhang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.
摘要翻译：电平转换器包括一个可编程的增强器级，在某些条件下增加电平转换器的驱动电平。增强级可编程激活。例如经由存储器单元或控制位，并且增加电平转换器内的交叉耦合锁存器的上拉级的操作。当电平转换器的高电压部分的电压电平降低到阈值电压以下时，升压级被激活，以维持电平转换器的正常工作，尽管降低了电压电平。

2. 发明授权

US07551646B1 Data alignment and deskewing module 有权
标题翻译：数据对齐和脱斜模块
公开(公告)号：US07551646B1
公开(公告)日：2009-06-23
申请号：US10938151
申请日：2004-09-10
申请人： Qi Zhang , Jason R. Bergendahl , Atul V. Ghia , Suresh M. Menon
发明人： Qi Zhang , Jason R. Bergendahl , Atul V. Ghia , Suresh M. Menon
IPC分类号： H04J3/06
CPC分类号： H04J3/0629
摘要： A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.
摘要翻译：数据对准和去歪斜模块包括延迟校准单元，数据对准和去歪斜单元以及延迟单元。延迟校准单元可操作地耦合以基于参考时钟和镜像延迟线输出信号产生参考信号。数据对准和去歪斜单元可操作地耦合以基于输入数据流的延迟和偏斜校正表示以及接收输入数据流的线的传播延迟来确定延迟选择信号。延迟单元可操作地耦合以基于参考信号和延迟选择信号产生输入数据流的延迟和去歪斜表示。

3. 发明授权

US07589557B1 Reversible input/output delay line for bidirectional input/output blocks 有权
标题翻译：用于双向输入/输出块的可逆输入/输出延迟线
公开(公告)号：US07589557B1
公开(公告)日：2009-09-15
申请号：US11405901
申请日：2006-04-18
申请人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
发明人： Jason R. Bergendahl , Qi Zhang , Jian Tan , Matthew H. Klein
IPC分类号： H03K19/173
CPC分类号： H03K5/159 , H03K19/017581 , H03K19/01759
摘要： An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.
摘要翻译：输入/输出（I / O）结构包括在用户设计中可用于输入路径，输出路径或输入和输出路径的延迟元件。在第一模式中，延迟元件包括在输入路径中。在第二模式中，延迟元件包括在输出路径中。在第三模式中，I / O结构包括输出信号路径和输入信号路径中的延迟，例如通过利用输出三态信号来控制延迟线的方向。当输出缓冲区正在驱动时，延迟被插入到输出路径中。当输出缓冲器被三态时，延迟被插入到输入路径中。因此，单个延迟元件由使用相同I / O焊盘的输入和输出信号动态共享。在可选的第四模式中，延迟元件被输入和输出信号旁路。

4. 发明授权

US07091890B1 Multi-purpose source synchronous interface circuitry 有权
标题翻译：多用途源同步接口电路
公开(公告)号：US07091890B1
公开(公告)日：2006-08-15
申请号：US10919901
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
发明人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0008
摘要： A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
摘要翻译：描述了在集成电路的可配置逻辑中实例化的串行器 - 解串器。串行器 - 解串器包括输入解串器和输出串行器，其可以通过输入/输出板通常耦合。串行器和解串器中的每一个可以被配置为从单数据速率模式和双数据速率模式中选择的操作模式。串行器 - 解串器可以用作同步接口的一部分。

5. 发明授权

US07502433B1 Bimodal source synchronous interface 有权
标题翻译：双模源同步接口
公开(公告)号：US07502433B1
公开(公告)日：2009-03-10
申请号：US10919766
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl
发明人： Paul T. Sasaki , Jason R. Bergendahl
IPC分类号： H04L7/00 , G06F1/12 , G06F13/42 , H03L7/00
CPC分类号： H04L7/0012 , G11C7/1078 , G11C7/1087 , G11C7/1093 , H04L7/0037 , H04L7/0041
摘要： Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input cell with a second delay chain and a second register block is provided for receipt of a data signal by the second delay chain. The second input cell is configured such that output from the second delay chain is coupled to a data input of the second register block. The first input cell and the second input cell may be operated in either a first modality or a second modality. The first modality may be for interfacing to a synchronous integrated circuit interface. The second modality may be for interfacing to a synchronous network/telecommunications interface.
摘要翻译：描述了用于接收器模块的双模源同步接口的方法和装置。提供具有第一延迟链和第一寄存器块的第一输入单元，用于由第一延迟链接收转发的时钟信号。提供具有第二延迟链和第二寄存器块的第二输入单元，用于由第二延迟链接收数据信号。第二输入单元被配置为使得来自第二延迟链的输出耦合到第二寄存器块的数据输入。第一输入单元和第二输入单元可以以第一模态或第二模态操作。第一种模式可以用于连接到同步集成电路接口。第二种模式可以用于连接到同步网络/电信接口。

6. 发明授权

US07353487B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07353487B1
公开(公告)日：2008-04-01
申请号：US10981877
申请日：2004-11-05
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。可编程逻辑器件包括全局信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

7. 发明授权

US06864715B1 Windowing circuit for aligning data and clock signals 有权
标题翻译：用于对准数据和时钟信号的窗口电路
公开(公告)号：US06864715B1
公开(公告)日：2005-03-08
申请号：US10377461
申请日：2003-02-27
申请人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
发明人： Trevor J. Bauer , Steven P. Young , Christopher D. Ebeling , Jason R. Bergendahl , Arthur J. Behiel
IPC分类号： G06F1/025 , H03K5/135 , H03K19/177 , H04L7/00 , G06F7/38 , H03D3/24 , H03K19/173
CPC分类号： H03K19/17764 , G06F1/025 , H03K5/135 , H03K19/1774 , H04L7/0004 , H04L7/0037 , H04L7/0041
摘要： Described are circuits and methods for aligning data and clock signals. Circuits in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.
摘要翻译：描述了用于对准数据和时钟信号的电路和方法。根据一些实施例的电路将输入数据分成三个不同定时的数据信号：早期信号，中间信号和后期信号。三个数据信号的定时可以相对于时钟信号共同移动。此外，可以调整三个信号之间的时间间隔，使得早期和晚期信号限定包围中间信号的窗口。三个信号相对于时钟边沿对齐，以使中间数据信号在时钟边沿居中。可以监视早期和晚期信号以识别时钟和数据信号的相对时序的变化。一些实施例自动改变数据和/或时钟信号的定时，以使中间数据信号以时钟边缘为中心。

8. 发明申请

US20200327271A1 FPGA Specialist Processing Block for Machine Learning 审中-公开
公开(公告)号：US20200327271A1
公开(公告)日：2020-10-15
申请号：US16914009
申请日：2020-06-26
申请人： Martin Langhammer , Dongdong Chen , Jason R. Bergendahl
发明人： Martin Langhammer , Dongdong Chen , Jason R. Bergendahl
IPC分类号： G06F30/34 , G06F30/38 , G06F9/30 , G06N20/00
摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

9. 发明授权

US06489837B2 Digitally controlled impedance for I/O of an integrated circuit device 有权
标题翻译：用于集成电路器件的I / O的数字控制阻抗
公开(公告)号：US06489837B2
公开(公告)日：2002-12-03
申请号：US10007167
申请日：2001-11-30
申请人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
发明人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
IPC分类号： G05F110
CPC分类号： H03K19/00384 , H03K19/0005 , H04L25/0278
摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.
摘要翻译：提供一种用于控制集成电路芯片上的电路的阻抗的系统。选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。选择其他电路用作电路和/或线路终端电路。数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。然后响应于该信息配置电路。

10. 发明授权

US06445245B1 Digitally controlled impedance for I/O of an integrated circuit device 有权
公开(公告)号：US06445245B1
公开(公告)日：2002-09-03
申请号：US09684539
申请日：2000-10-06
申请人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
发明人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
IPC分类号： G05F110
CPC分类号： H03K19/00384 , H03K19/0005 , H04L25/0278
摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式