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1. 发明授权

US07502433B1 Bimodal source synchronous interface 有权
标题翻译：双模源同步接口
公开(公告)号：US07502433B1
公开(公告)日：2009-03-10
申请号：US10919766
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl
发明人： Paul T. Sasaki , Jason R. Bergendahl
IPC分类号： H04L7/00 , G06F1/12 , G06F13/42 , H03L7/00
CPC分类号： H04L7/0012 , G11C7/1078 , G11C7/1087 , G11C7/1093 , H04L7/0037 , H04L7/0041
摘要： Method and apparatus for a bimodal source synchronous interface for a receiver module is described. A first input cell with a first delay chain and a first register block is provided for receipt of a forwarded clock signal by the first delay chain. A second input cell with a second delay chain and a second register block is provided for receipt of a data signal by the second delay chain. The second input cell is configured such that output from the second delay chain is coupled to a data input of the second register block. The first input cell and the second input cell may be operated in either a first modality or a second modality. The first modality may be for interfacing to a synchronous integrated circuit interface. The second modality may be for interfacing to a synchronous network/telecommunications interface.
摘要翻译：描述了用于接收器模块的双模源同步接口的方法和装置。提供具有第一延迟链和第一寄存器块的第一输入单元，用于由第一延迟链接收转发的时钟信号。提供具有第二延迟链和第二寄存器块的第二输入单元，用于由第二延迟链接收数据信号。第二输入单元被配置为使得来自第二延迟链的输出耦合到第二寄存器块的数据输入。第一输入单元和第二输入单元可以以第一模态或第二模态操作。第一种模式可以用于连接到同步集成电路接口。第二种模式可以用于连接到同步网络/电信接口。

2. 发明授权

US07353487B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07353487B1
公开(公告)日：2008-04-01
申请号：US10981877
申请日：2004-11-05
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。可编程逻辑器件包括全局信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

3. 发明授权

US07617472B1 Regional signal-distribution network for an integrated circuit 有权
标题翻译：集成电路的区域信号分配网络
公开(公告)号：US07617472B1
公开(公告)日：2009-11-10
申请号：US12025637
申请日：2008-02-04
申请人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
发明人： Jason R. Bergendahl , Ping-Chen Liu , Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Steven P. Young , Trevor J. Bauer
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.
摘要翻译：描述区域信号的信号分布。集成电路包括全球信号分配网络，区域信号分配网络和区域缓冲器。区域缓冲区具有耦合在区域信号分配网络末端的输出。区域信号分配网络通过互连瓦片耦合到可配置的逻辑块。区域缓冲器耦合到具有区域时钟的输入/输出块。另外描述了用于区域信号分配的源同步接口。

4. 发明授权

US07091890B1 Multi-purpose source synchronous interface circuitry 有权
标题翻译：多用途源同步接口电路
公开(公告)号：US07091890B1
公开(公告)日：2006-08-15
申请号：US10919901
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
发明人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Hassan Bazargan , Ketan Sodha , Jian Tan , Qi Zhang , Suresh Menon
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0008
摘要： A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
摘要翻译：描述了在集成电路的可配置逻辑中实例化的串行器 - 解串器。串行器 - 解串器包括输入解串器和输出串行器，其可以通过输入/输出板通常耦合。串行器和解串器中的每一个可以被配置为从单数据速率模式和双数据速率模式中选择的操作模式。串行器 - 解串器可以用作同步接口的一部分。

5. 发明授权

US06985096B1 Bimodal serial to parallel converter with bitslip controller 有权
标题翻译：双模串行到并行转换器与位滑控制器
公开(公告)号：US06985096B1
公开(公告)日：2006-01-10
申请号：US10919900
申请日：2004-08-17
申请人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Jian Tan
发明人： Paul T. Sasaki , Jason R. Bergendahl , Atul Ghia , Jian Tan
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135
摘要： Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.
摘要翻译：提供了一种双模串并转换器的方法和装置。响应于时钟信号（诸如同步接口的转发时钟信号）对寄存器的第一级进行时钟控制。寄存器的第一级可以在单个串行移位链或两个串行移位链中进行配置。前一种配置用于单数据速率（“SDR”）数据，后一种配置用于双倍数据速率（“DDR”）数据。位位控制器被配置为向选择电路提供控制选择信号。对于DDR操作，控制信号用于选择来自两个串行移位链的输出的相应部分以提供给第二级寄存器。对于DDR操作，响应于时钟信号的分频版本和周期性地停止的时钟信号的另一个分频模式，寄存器的第二级可选地进行时钟控制。

6. 发明授权

US07111220B1 Network physical layer with embedded multi-standard CRC generator 有权
标题翻译：具有嵌入式多标准CRC发生器的网络物理层
公开(公告)号：US07111220B1
公开(公告)日：2006-09-19
申请号：US10090519
申请日：2002-03-01
申请人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
发明人： Paul T. Sasaki , Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Hare K. Verma , Philip M. Freidin
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6519 , H04L69/32 , H04L69/324
摘要： Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.
摘要翻译：公开了用于准备通过网络传输的数据的方法和结构。在与OSI网络模型一致的实施例中，发送和接收CRC发生器从链路层移动到物理层，当使用可编程逻辑器件来执行链路层的功能时，发送和接收CRC发生器释放有价值的可编程逻辑资源。物理层的CRC生成器符合多个网络通信标准。

7. 发明授权

US06960933B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06960933B1
公开(公告)日：2005-11-01
申请号：US10618146
申请日：2003-07-11
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19/177 , H04L25/45
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

8. 发明授权

US06617877B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device 有权
标题翻译：可编程逻辑器件上的千兆位收发器中的可变数据宽度操作
公开(公告)号：US06617877B1
公开(公告)日：2003-09-09
申请号：US10090286
申请日：2002-03-01
申请人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
发明人： Warren E. Cory , Hare K. Verma , Atul V. Ghia , Paul T. Sasaki , Suresh M. Menon
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744 , H04L25/45
摘要： A transmit variable-width interface can be programmed to convert an electronic digital data path that is either 1N, 2N, 4N, or 8N bits wide into a data path that is 2N bits wide, either by serializing bits (4N- or 8N-bit cases), re-clocking bits (2N-bit case), or grouping bits (1N-bit case). A receive variable-width interface can be programmed to convert a data path 2N bits wide into a data path that is 1N, 2N, 4N, or 8N bits wide. The widths of the two variable-width data paths are controlled independently. The variable-width interfaces are coupled between a multi-gigabit transceiver and core logic of a programmable logic device. The incoming and outgoing data paths of the variable-width interfaces have separate clocks signals that are synchronized such that small amounts of skew in these clock signals do not disrupt the operation of the variable-width interfaces.
摘要翻译：传输可变宽度接口可编程为将1N，2N，4N或8N位宽的电子数字数据路径转换为2N位宽的数据通道，通过将位（4N或8N位）情况），重新计时位（2N位情况）或分组位（1N位情况）。接收可变宽度接口可以被编程为将2N位宽的数据路径转换成1N，2N，4N或8N位宽的数据路径。两个可变宽度数据路径的宽度被独立地控制。可变宽度接口耦合在可编程逻辑器件的千兆位收发器和核心逻辑之间。可变宽度接口的输入和输出数据路径具有同步的分离时钟信号，使得这些时钟信号中的少量偏移不会中断可变宽度接口的操作。

9. 发明授权

US07187709B1 High speed configurable transceiver architecture 有权
标题翻译：高速可配置收发器架构
公开(公告)号：US07187709B1
公开(公告)日：2007-03-06
申请号：US10090250
申请日：2002-03-01
申请人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
发明人： Suresh M. Menon , Atul V. Ghia , Warren E. Cory , Paul T. Sasaki , Philip M. Freidin , Santiago G. Asuncion , Philip D. Costello , Vasisht M. Vadi , Adebabay M. Bekele , Hare K. Verma
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G06F15/7867
摘要： One or more configurable transceivers can be fabricated on an integrated circuit. The transceivers contain various components having options that can be configured by turning configuration memory cells on or off. The integrated circuit may also contain programmable fabric. Other components in the transceivers can have options that are controlled by the programmable fabric. The integrated circuit may also contain one or more processor cores. The processor core and the transceivers can be connected by a plurality of signal paths that pass through the programmable fabric.
摘要翻译：一个或多个可配置的收发器可以在集成电路上制造。收发器包含各种组件，具有可通过打开或关闭配置存储单元来配置的选项。该集成电路还可以包含可编程织物。收发器中的其他组件可以具有由可编程结构控制的选项。集成电路还可以包含一个或多个处理器核。处理器核心和收发器可以通过通过可编程结构的多个信号路径连接。

10. 发明授权

US06218856B1 High speed programmable logic architecture 失效
标题翻译：高速可编程逻辑架构
公开(公告)号：US06218856B1
公开(公告)日：2001-04-17
申请号：US08731369
申请日：1996-10-11
申请人： Paul T. Sasaki
发明人： Paul T. Sasaki
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17704 , H03K19/17728 , H03K19/17784 , H03K19/17792
摘要： Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable active driver circuits are employed. These circuits eliminate essentially all of the resistance present in prior art passive connections.
摘要翻译：描述了可编程逻辑器件的架构，其可以以比当前可编程逻辑器件更快的时钟速率工作。代替采用无源电路元件来互连可编程逻辑元件和输入和输出数据总线，采用可控的有源驱动器电路。这些电路基本消除了现有技术无源连接中存在的所有电阻。

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