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1. 发明申请

US20120011304A1 ENHANCED ADDRESSABILITY FOR SERIAL NON-VOLATILE MEMORY 有权
标题翻译：增强串行非易失性存储器的可访问性
公开(公告)号：US20120011304A1
公开(公告)日：2012-01-12
申请号：US13143072
申请日：2008-12-30
申请人： Poorna Kale , Chris Bueb , Tommaso Zerilli , Raffaele Bufano , Sandra Lospalluti , Marco Gibilaro
发明人： Poorna Kale , Chris Bueb , Tommaso Zerilli , Raffaele Bufano , Sandra Lospalluti , Marco Gibilaro
IPC分类号： G06F12/02
CPC分类号： G11C16/08 , G11C8/12 , G11C16/26 , G11C2216/30
摘要： Example embodiments for providing enhanced addressability for a serial non-volatile memory device may comprise accessing a storage location based, at least in part, on an extended address value and an address, the extended address value to identify a subset of storage locations from a plurality of storage locations, the address to identify the storage location within the subset of storage locations.
摘要翻译：用于为串行非易失性存储器设备提供增强的寻址能力的示例性实施例可以包括至少部分地基于扩展地址值和地址来访问存储位置，扩展地址值以从多个区域识别存储位置的子集的存储位置，用于识别存储位置子集内的存储位置的地址。

2. 发明授权

US08607028B2 Enhanced addressability for serial non-volatile memory 有权
标题翻译：增强了串行非易失性存储器的寻址能力
公开(公告)号：US08607028B2
公开(公告)日：2013-12-10
申请号：US13143072
申请日：2008-12-30
申请人： Poorna Kale , Chris Bueb , Tommaso Zerilli , Raffaele Bufano , Sandra Lospalluti , Marco Gibilaro
发明人： Poorna Kale , Chris Bueb , Tommaso Zerilli , Raffaele Bufano , Sandra Lospalluti , Marco Gibilaro
IPC分类号： G06F12/00
CPC分类号： G11C16/08 , G11C8/12 , G11C16/26 , G11C2216/30
摘要： A method and a memory device are provided for accessing a storage location. The method includes storing an extended address value in a register in a non-volatile memory device. The method further includes subsequently receiving multiple addresses and combining the stored extended address value with each of the multiple received addresses to produce multiple combined addresses. The method further includes accessing multiple storage locations within the non-volatile memory device based, at least in part, on the multiple combined addresses.
摘要翻译：提供了一种用于访问存储位置的方法和存储装置。该方法包括将扩展地址值存储在非易失性存储器件中的寄存器中。该方法还包括随后接收多个地址并将存储的扩展地址值与多个接收的地址中的每一个组合以产生多个组合的地址。该方法还包括至少部分地基于多个组合地址访问非易失性存储器设备内的多个存储位置。

3. 发明授权

US08626990B2 Non-volatile configuration for serial non-volatile memory 有权
标题翻译：用于串行非易失性存储器的非易失性配置
公开(公告)号：US08626990B2
公开(公告)日：2014-01-07
申请号：US13143075
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/44573 , G06F2212/72 , G11C16/10 , G11C16/20
摘要： Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置串行非易失性存储器设备的示例性实施例可以包括用于存储从处理器接收的配置值的非易失性配置寄存器，该配置值指定存储器访问操作的一个或多个属性。至少部分地响应于施加到存储器件的功率来读取配置值。

4. 发明授权

US08635398B2 Execute-in-place mode configuration for serial non-volatile memory 有权
标题翻译：串行非易失性存储器的就地模式配置
公开(公告)号：US08635398B2
公开(公告)日：2014-01-21
申请号：US13143078
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/30098 , G06F9/44573 , G06F2212/72 , G06F2212/7206 , G11C16/26 , G11C2216/30
摘要： Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置用于就地执行模式的串行非易失性存储器件的示例性实施例可以包括非易失性配置寄存器，用于存储至少部分地响应于功率而被读取的就地执行模式值应用于存储器件。

5. 发明申请

US20120110246A1 EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY 有权
标题翻译：串行非易失性存储器的EXECUTE-IN-PLACE MODE CONFIGURATION
公开(公告)号：US20120110246A1
公开(公告)日：2012-05-03
申请号：US13143078
申请日：2008-12-30
申请人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
发明人： Paolo Rolandi , Sandra Lospalluti , Raffaele Bufano , Stefano Andreoli , Tommaso Zerilli
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F9/30098 , G06F9/44573 , G06F2212/72 , G06F2212/7206 , G11C16/26 , G11C2216/30
摘要： Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.
摘要翻译：用于配置用于就地执行模式的串行非易失性存储器件的示例性实施例可以包括非易失性配置寄存器，用于存储至少部分地响应于功率而被读取的就地执行模式值应用于存储器件。

6. 发明授权

US6130844A Low consumption boosted voltage driving circuit 有权
标题翻译：低功耗升压电压驱动电路
公开(公告)号：US6130844A
公开(公告)日：2000-10-10
申请号：US257682
申请日：1999-02-26
申请人： Tommaso Zerilli , Maurizio Gaibotti
发明人： Tommaso Zerilli , Maurizio Gaibotti
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C8/08
摘要： A boosted voltage driving circuit includes an inverter circuit with positive feedback and a selective breaking circuit. The selective breaking circuit disconnects the positive feedback from the output load during an operation phase of the boosted voltage driving circuit in order to reduce energy consumption. In a preferred embodiment, the boosted voltage driving circuit is the final stage of a decoder circuit for selecting and deselecting a line or column of a memory array, and the positive feedback is disconnected during a deselection phase in which the line or column is deselected. The present invention also provides a boosted voltage driving circuit that includes first, second, and third transistors and a selective breaking circuit. The first transistor is connected between a supply voltage and an output node, the second transistor is connected between the output node and ground, and the third transistor is connected between the supply voltage and the gate of the first transistor. Further, the selective breaking circuit is connected between the output node and the gate of the third transistor to disconnect the gate of the third transistor from the output node during an operation phase of the boosted voltage driving circuit.
摘要翻译：升压电压驱动电路包括具有正反馈的反相器电路和选择性分断电路。选择性分断电路在升压电压驱动电路的运行阶段将正反馈与输出负载断开，以便降低能耗。在优选实施例中，升压电压驱动电路是用于选择和取消选择存储器阵列的行或列的解码器电路的最后一级，并且在取消选择行或列的取消选择阶段中断开正反馈。本发明还提供一种包括第一，第二和第三晶体管和选择性分断电路的升压电压驱动电路。第一晶体管连接在电源电压和输出节点之间，第二晶体管连接在输出节点和地之间，第三晶体管连接在电源电压和第一晶体管的栅极之间。此外，选择性分断电路连接在第三晶体管的输出节点和栅极之间，以在升压电压驱动电路的操作阶段期间将第三晶体管的栅极与输出节点断开。

7. 发明授权

US06288960B1 Bias circuit for read amplifier circuits for memories 有权
标题翻译：用于存储器的读取放大器电路的偏置电路
公开(公告)号：US06288960B1
公开(公告)日：2001-09-11
申请号：US09686326
申请日：2000-10-11
申请人： Antonino Conte , Maurizio Gaibotti , Tommaso Zerilli
发明人： Antonino Conte , Maurizio Gaibotti , Tommaso Zerilli
IPC分类号： G11C700
CPC分类号： G11C7/14 , G11C7/062
摘要： A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.
摘要翻译：用于存储器的读取放大器电路的偏置电路包括由连接在电源电压和地之间的第一对MOS晶体管形成的至少一个第一电路支路。第一对MOS晶体管包括串联连接的P沟道二极管晶体管和N沟道晶体管，其间插入有使能晶体管。第一个电路分支驱动电容性负载以耦合到电源电压。偏置电路还包括用于放大在第一电路支路中流动以对电容性负载充电的参考电流的参考电流放大器电路分支。控制电容性负载的充电电流的电路部分包括参考电流放大器电路分支和容性负载之间的反馈回路。

8. 发明授权

US06650153B2 Generator circuit for voltage ramps and corresponding voltage generation method 有权
公开(公告)号：US06650153B2
公开(公告)日：2003-11-18
申请号：US10033711
申请日：2001-12-28
申请人： Tommaso Zerilli , Maurizio Gaibotti
发明人： Tommaso Zerilli , Maurizio Gaibotti
IPC分类号： H03K406
CPC分类号： H03K17/163 , H03K4/00
摘要： A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

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