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1. 发明授权

US07287325B2 Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing 失效
标题翻译：使用后化学机械抛光形成互连结构或互连和通孔结构的方法
公开(公告)号：US07287325B2
公开(公告)日：2007-10-30
申请号：US10908392
申请日：2005-05-10
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01K3/10
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

2. 发明授权

US07473636B2 Method to improve time dependent dielectric breakdown 失效
标题翻译：改善时间依赖介电击穿的方法
公开(公告)号：US07473636B2
公开(公告)日：2009-01-06
申请号：US11306825
申请日：2006-01-12
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Vincent J. McGahay , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76846 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.
摘要翻译：在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

3. 发明授权

US08465657B2 Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability 有权
标题翻译：后化学机械抛光蚀刻，以提高时间依赖的介电击穿可靠性
公开(公告)号：US08465657B2
公开(公告)日：2013-06-18
申请号：US11833283
申请日：2007-08-03
申请人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
发明人： Kaushik Chanda , James J. Demarest , Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewara , Ping-Chuan Wang , Yun-Yu Wang
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： B24B37/042 , H01L21/31144 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L21/76852 , H01L21/76885 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204
摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.
摘要翻译：公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。释放层沉积在电介质层上。释放层包括有机材料，电介质材料，金属或金属氮化物。沟槽蚀刻到电介质层中。沟槽内衬衬里，填充导体。导体和衬里材料从剥离层抛光。然而，痕量的剩余材料可能会残留。去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

4. 发明授权

US06383920B1 Process of enclosing via for improved reliability in dual damascene interconnects 有权
标题翻译：封装通孔的过程可提高双镶嵌互连中的可靠性
公开(公告)号：US06383920B1
公开(公告)日：2002-05-07
申请号：US09757894
申请日：2001-01-10
申请人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
发明人： Ping-Chuan Wang , Ronald G. Filippi , Robert D. Edwards , Edward W. Kiewra , Roy C. Iggulden
IPC分类号： H01L214763
CPC分类号： H01L21/76847 , H01L21/76807 , H01L21/76811 , H01L21/76813 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.
摘要翻译：本发明一般涉及在双镶嵌工艺中封闭通孔的方法。在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在双镶嵌工艺。阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

5. 发明授权

US07361584B2 Detection of residual liner materials after polishing in damascene process 失效
标题翻译：在镶嵌工艺中抛光后残留衬垫材料的检测
公开(公告)号：US07361584B2
公开(公告)日：2008-04-22
申请号：US10904329
申请日：2004-11-04
申请人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Stephen K. Loh , Ping-Chuan Wang
发明人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Stephen K. Loh , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/7688 , H01L22/24 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.
摘要翻译：用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。此外，标记层包括与电介质层分离的层。另外，紫外线可检测材料包括荧光材料或磷光材料。

6. 发明授权

US07560375B2 Gas dielectric structure forming methods 失效
标题翻译：气体介电结构成型方法
公开(公告)号：US07560375B2
公开(公告)日：2009-07-14
申请号：US10711697
申请日：2004-09-30
申请人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
发明人： Ronald G. Filippi , Roy C. Iggulden , Edward W. Kiewra , Ping-Chuan Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.
摘要翻译：通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

7. 发明授权

US06870263B1 Device interconnection 失效
标题翻译：设备互连
公开(公告)号：US06870263B1
公开(公告)日：2005-03-22
申请号：US09052688
申请日：1998-03-31
申请人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
发明人： Lawrence A. Clevenger , Ronald G. Filippi , Mark Hoinkis , Jeffery L. Hurd , Roy C. Iggulden , Herbert Palm , Hans W. Poetzlberger , Kenneth P. Rodbell , Florian Schnabel , Stefan Weber , Ebrahim A. Mehter
IPC分类号： H01L21/28 , H01L21/768 , H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.
摘要翻译：用于互连具有改进的可靠性的集成电路部件的导体。导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。已经发现，低纹理导体导致改善的电迁移寿命。

8. 发明授权

US06734097B2 Liner with poor step coverage to improve contact resistance in W contacts 有权
标题翻译：衬垫差步幅覆盖，以提高W触点的接触电阻
公开(公告)号：US06734097B2
公开(公告)日：2004-05-11
申请号：US09965094
申请日：2001-09-28
申请人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
发明人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.
摘要翻译：一种用衬垫填充镶嵌结构的方法，其特征在于改进的阻力和阻力扩展以及足够的粘合性，其包括：由衬垫涂覆的给定镶嵌结构，其有目的地为上述结构提供差的步骤覆盖，随后进行CVD W沉积，其次是金属隔离技术。

9. 发明授权

US06635564B1 Semiconductor structure and method of fabrication including forming aluminum columns 有权
标题翻译：半导体结构和制造方法，包括形成铝柱
公开(公告)号：US06635564B1
公开(公告)日：2003-10-21
申请号：US09662424
申请日：2000-09-14
申请人： Stefan Weber , Roy C. Iggulden
发明人： Stefan Weber , Roy C. Iggulden
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76876 , H01L21/76885 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C. to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer (34). The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.
摘要翻译：在覆盖半导体衬底（主体）的第一绝缘层中形成的高纵横比通孔以两种方式填充有导体，这两者都减少了加工步骤的数量，并允许对准工具（步进器）对准定位和重叠标记。每个通孔的侧壁和底部涂覆有钛，氮化钛和化学气相沉积的铝层的复合层。然后在将结构加热至约400℃的同时形成铝的物理气相沉积层，以完全填充通孔并过度填充其，以在第一绝缘层（34）上方形成覆盖层的铝。然后将铝的覆盖层图案化，并且去除不被图案覆盖的部分以产生铝列。然后围绕铝列形成第二绝缘层。在第二绝缘层的顶部的列的端部位于相对公平的平面中，步进器可以相对容易地对准图案。

10. 发明授权

US06413866B1 Method of forming a solute-enriched layer in a substrate surface and article formed thereby 有权
标题翻译：在基材表面形成富含溶质层的方法和由此形成的制品
公开(公告)号：US06413866B1
公开(公告)日：2002-07-02
申请号：US09525367
申请日：2000-03-15
申请人： Horatio S. Wildman , Lawrence A. Clevenger , Chenting Lin , Kenneth P. Rodbell , Stefan Weber , Roy C. Iggulden , Maria Ronay , Florian Schnabel
发明人： Horatio S. Wildman , Lawrence A. Clevenger , Chenting Lin , Kenneth P. Rodbell , Stefan Weber , Roy C. Iggulden , Maria Ronay , Florian Schnabel
IPC分类号： H01L2144
CPC分类号： H01L21/7685 , H01L21/321 , H01L21/76867 , H01L21/76888 , H01L23/53219 , H01L2924/0002 , H01L2924/00
摘要： A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.
摘要翻译：一种使用最初溶解在基片材料中的溶质材料来富集基片的表面的方法，以使溶质材料在基片表面上均匀分散。该方法通常需要使用比溶质材料对选择的反应剂更具反应性的溶剂材料。使基板的表面与反应剂反应，以优先在基材的表面形成溶剂材料的反应化合物。当化合物层发展时，溶质材料从化合物层中分离或扩散到下面的衬底中，使得最接近化合物层的衬底的区域变得富集溶质材料。然后除去化合物层的至少一部分而不去除底物的下面的富集区域。对于微电路应用，该方法可用于通过元素铜来丰富铝线的表面，以提高线路的电迁移能力。

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