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1. 发明授权

US06815307B1 Method for fabricating a deep trench capacitor 有权
标题翻译：深沟槽电容器的制造方法
公开(公告)号：US06815307B1
公开(公告)日：2004-11-09
申请号：US10605217
申请日：2003-09-16
申请人： Ping Hsu , Tzu-Ching Tsai
发明人： Ping Hsu , Tzu-Ching Tsai
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： This invention pertains to a method for making a trench capacitor of DRAM devices. A portion of the collar oxide layer is masked after the second polysilicon deposition and recess etching process. Subsequently, the un-masked collar oxide layer is etched away to form an asymmetric collar oxide structure. The third polysilicon deposition and recess etching process is then carried out to form a third polysilicon stud atop the second polysilicon layer. The asymmetric collar oxide structure has a lower annular portion wrapping the second polysilicon layer and insulating the second polysilicon layer from the substrate, and an upper portion serving as a single-sided spacer for blocking diffusion of dopants from the third polysilicon stud to the substrate.

2. 发明授权

US06831016B2 Method to prevent electrical shorts between adjacent metal lines 有权
标题翻译：防止相邻金属线之间电气短路的方法
公开(公告)号：US06831016B2
公开(公告)日：2004-12-14
申请号：US10153347
申请日：2002-05-21
申请人： Tzu-Ching Tsai , Ping Hsu
发明人： Tzu-Ching Tsai , Ping Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/7684
摘要： A method to prevent electrical shorts between adjacent metal lines on a semiconductor substrate having an insulating layer with a pair of damascene structures connecting to the semiconductor substrate and a scratch on the upper surface of the insulating layer, between the damascene structures, is provided. A diffusion barrier layer is deposited on the damascene structures and the scratch. Then, a metal layer is formed to fill the damascene structures. Next, the metal is chemical-mechanically polished to form a metal line. Finally, the diffusion barrier layer disposed on the surface of the scratch is removed by etching process.
摘要翻译：提供了防止在具有绝缘层的半导体衬底上的相邻金属线之间的电短路的方法，所述绝缘层具有连接到半导体衬底的一对镶嵌结构和在镶嵌结构之间的绝缘层的上表面上的划痕。扩散阻挡层沉积在镶嵌结构和划痕上。然后，形成金属层以填充镶嵌结构。接下来，金属被化学机械抛光以形成金属线。最后，通过蚀刻工艺去除设置在划痕表面上的扩散阻挡层。

3. 发明申请

US20120302060A1 METHOD FOR MANUFACTURING MEMORY DEVICE 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120302060A1
公开(公告)日：2012-11-29
申请号：US13115039
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L27/10873 , H01L21/76834 , H01L21/7684 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
摘要翻译：本公开提供了一种用于制造存储器件的方法，包括：提供形成在衬底上的多个栅极结构，其中栅极结构包括设置在栅极结构的顶部上的覆盖层，并且每个两个相邻的栅极结构由一个沟; 在基底上覆盖地形成多晶硅层以填补间隙; 对多晶硅层进行平坦化处理，获得多晶硅插塞; 并且在平坦化处理之后进行氧化处理，将多晶硅插塞的一部分和栅极结构上的剩余多晶硅层转换成氧化硅。

4. 发明申请

US20120302049A1 METHOD FOR IMPLANTING WAFER 审中-公开
标题翻译：埋植方法
公开(公告)号：US20120302049A1
公开(公告)日：2012-11-29
申请号：US13115030
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/265
CPC分类号： H01L21/26513
摘要： The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different.
摘要翻译：本公开提供了一种用于晶片植入的方法，包括以下步骤：提供晶片，其中晶片包括中心圆形部分和与晶片边缘相邻的外围环形部分，并且其中中心圆形部分和周边环形部分是同心的以及将离子束注入到所述晶片中，其中所述中心圆形部分具有第一平均植入剂量，并且所述周边环形部分具有第二平均植入剂量，并且所述第一平均植入剂量和所述第二平均植入剂量是不同的。

5. 发明申请

US20120295408A1 METHOD FOR MANUFACTURING MEMORY DEVICE 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120295408A1
公开(公告)日：2012-11-22
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

6. 发明申请

US20050247930A1 Shallow trench isolation void detecting method and structure for the same 审中-公开
标题翻译：浅沟隔离空洞检测方法和结构相同
公开(公告)号：US20050247930A1
公开(公告)日：2005-11-10
申请号：US11179518
申请日：2005-07-13
申请人： Ping Hsu , Yi-Nan Chen
发明人： Ping Hsu , Yi-Nan Chen
IPC分类号： G01R31/28 , G11C29/00 , H01L21/762 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , G01R31/2884 , G11C29/006 , H01L21/76224
摘要： Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.
摘要翻译：披露的是检测半导体晶片的STI空隙的方法。本发明的方法包括以下步骤：在晶片的预定区域中分配检测区域; 通过与晶片的其它区域同步的工艺形成与有源区域交叉的有源区和栅极条。电介质材料填充在有源区域之间。有效区域之间的相邻部分至少达到预定长度。测量栅极条的电气值以确定在有源区域之间填充的电介质是否存在任何空隙，由此导出在晶片的其它区域的有源区域之间在STI中产生的任何空隙。

7. 发明申请

US20050158972A1 Method for manufacturing bit line contact structure of semiconductor memory 审中-公开
标题翻译：半导体存储器的位线接触结构的制造方法
公开(公告)号：US20050158972A1
公开(公告)日：2005-07-21
申请号：US10759058
申请日：2004-01-20
申请人： Feng-Chuan Lin , Yi-Nan Chen , Ping Hsu
发明人： Feng-Chuan Lin , Yi-Nan Chen , Ping Hsu
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10888
摘要： A method is disclosed for manufacturing bit line contact structures of semiconductor memories. The manufacturing method comprises the steps of providing a semiconductor substrate, forming a plurality of gates on the surface of the substrate, applying a first insulating layer to cover the surface of the substrate and the gates, selectively forming a plurality of gate contact windows at the locations of the gates, selectively forming bit line contact windows in the first insulating layer, the bit line contact windows contacting the substrate, and filling the gate contact windows and the bit line contact windows with a conductive layer.
摘要翻译：公开了一种用于制造半导体存储器的位线接触结构的方法。该制造方法包括以下步骤：提供半导体衬底，在衬底的表面上形成多个栅极，施加第一绝缘层以覆盖衬底和栅极的表面，并选择性地形成多个栅极接触窗口栅极的位置，在第一绝缘层中选择性地形成位线接触窗口，与衬底接触的位线接触窗口，以及用导电层填充栅极接触窗口和位线接触窗口。

8. 发明申请

US20050153506A1 ISOLATION STRUCTURE FOR TRENCH CAPACITORS AND FABRICATION METHOD THEREOF 有权
标题翻译： TRENCH电容器的隔离结构及其制造方法
公开(公告)号：US20050153506A1
公开(公告)日：2005-07-14
申请号：US10904593
申请日：2004-11-18
申请人： Yinan Chen , Ping Hsu , Li-Han Lu
发明人： Yinan Chen , Ping Hsu , Li-Han Lu
IPC分类号： H01L21/20 , H01L21/762 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L21/76232 , H01L27/0214 , H01L27/10861 , H01L27/10867
摘要： This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxide layer of the trench capacitor remain intact during the etching processes.
摘要翻译：本发明涉及一种用于自对准制造沟槽电容器隔离结构的方法。该方法需要两个步骤来蚀刻用于形成隔离结构的浅沟槽的衬底，其中沟槽电容器的导电层和套环氧化物层在蚀刻工艺期间保持完整。

9. 发明授权

US06821844B2 Collar dielectric process for reducing a top width of a deep trench 有权
标题翻译：用于减小深沟槽顶部宽度的套圈电介质工艺
公开(公告)号：US06821844B2
公开(公告)日：2004-11-23
申请号：US10643169
申请日：2003-08-18
申请人： Ping Hsu
发明人： Ping Hsu
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： A collar dielectric process for reducing a top width of a deep trench. A semiconductor silicon substrate has a deep trench and a deep trench capacitor. The deep trench capacitor has a node dielectric formed on the sidewall and bottom of the deep trench, and a storage node formed in the deep trench and reaching a predetermined depth. An ion implantation process is performed to form an ion implantation area on the substrate at the top of the deep trench. Then, the node dielectric is removed until the top of the node dielectric is leveled off with the top of the storage node, thus exposing the sidewall of the deep trench outside the deep trench capacitor. Next, an oxidation process is performed to grow a first silicon oxide layer on the exposed sidewall of the deep trench, in which the first silicon layer is outside the ion implantation area.
摘要翻译：用于减小深沟槽的顶部宽度的套环电介质方法。半导体硅衬底具有深沟槽和深沟槽电容器。深沟槽电容器具有形成在深沟槽的侧壁和底部上的节点电介质和形成在深沟槽中并达到预定深度的存储节点。执行离子注入工艺以在深沟槽顶部的衬底上形成离子注入区。然后，去除节点电介质，直到节点电介质的顶部与存储节点的顶部平齐，从而暴露深沟槽的侧壁在深沟槽电容器外部。接下来，进行氧化处理以在深沟槽的暴露的侧壁上生长第一氧化硅层，其中第一硅层在离子注入区域的外部。

10. 发明申请

US20060292775A1 Method of manufacturing DRAM capable of avoiding bit line leakage 审中-公开
标题翻译：制造能够避免位线泄漏的DRAM的方法
公开(公告)号：US20060292775A1
公开(公告)日：2006-12-28
申请号：US11167168
申请日：2005-06-28
申请人： Ping Hsu , Yinan Chen , Wen-Hsiung Chang
发明人： Ping Hsu , Yinan Chen , Wen-Hsiung Chang
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/02074 , H01L21/32134 , H01L21/32136 , H01L21/76816 , H01L21/7684 , H01L27/10888
摘要： A method to make DRAM capable of avoiding bit line leakage is provided. The method comprise the steps of forming transistors on substrate, forming an insulating layer to cover the substrate and the transistors, forming a poly-silicon layer over the insulating layer, forming contact holes in the poly-silicon layer and the insulating layer, the contact holes touching the substrate, filling the contact holes with a conducting layer, and etching the surface of the conducting layer with O2/O3 plasma or an etchant of H2SO4, H2O2 and HF.
摘要翻译：提供了一种能够避免位线泄漏的DRAM的方法。该方法包括以下步骤：在衬底上形成晶体管，形成绝缘层以覆盖衬底和晶体管，在绝缘层上形成多晶硅层，在多晶硅层和绝缘层中形成接触孔，接触接触基板的孔，用导电层填充接触孔，并用O 2 O 3 O 3等离子体蚀刻导电层的表面或H

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