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1. 发明申请

US20050104063A1 Shallow trench isolation void detecting method and structure for the same 有权
公开(公告)号：US20050104063A1
公开(公告)日：2005-05-19
申请号：US10714952
申请日：2003-11-18
申请人： Ping Hsu , Yi-Nan Chen
发明人： Ping Hsu , Yi-Nan Chen
IPC分类号： G01R31/28 , G11C29/00 , H01L21/762 , H01L23/544 , H01L21/66 , G01R31/26 , H01L23/58 , H01L29/10
CPC分类号： H01L22/34 , G01R31/2884 , G11C29/006 , H01L21/76224
摘要： Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.

2. 发明申请

US20120293196A1 TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF 审中-公开
标题翻译：用于监控门电导体深度偏差的测试关键结构及其测试方法
公开(公告)号：US20120293196A1
公开(公告)日：2012-11-22
申请号：US13111714
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/2644 , G01R31/2884
摘要： The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately.
摘要翻译：本公开提供了用于监视栅极导体到深沟槽未对准的测试键结构及其测试方法。用于监控栅极导体到深沟槽未对准的测试键结构包括：深沟槽电容器结构，其包括多个平行深沟槽电容器线和深沟槽电容器连接; 邻近深沟槽电容器线的第一侧的掩埋带外扩散; 包括多个平行的第一栅极导体线和第一栅极导体连接的第一栅极导体结构，其中每个第一栅极导线直接设置在相应的深沟槽电容器线上方; 以及包括多个平行的第二栅极导体线和第二栅极导体连接的第二栅极导体结构，其中所述第一栅极导体线经由所述第二栅极导体连接彼此电连接，并且其中所述第一栅极导体线和第二栅极导体线彼此平行，并且第一栅极导体线和第二栅极导体线交替布置。

3. 发明申请

US20050151182A1 ISOLATION STRUCTURE FOR TRENCH CAPACITORS AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： TRENCH电容器的隔离结构及其制造方法
公开(公告)号：US20050151182A1
公开(公告)日：2005-07-14
申请号：US10707805
申请日：2004-01-13
申请人： Yi-Nan Chen , Ping Hsu , Li-Han Lu
发明人： Yi-Nan Chen , Ping Hsu , Li-Han Lu
IPC分类号： H01L21/20 , H01L21/762 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L21/76232 , H01L27/0214 , H01L27/10861 , H01L27/10867
摘要： An isolation structure of a trench capacitor of DRAM has a first isolation portion covering the trench capacitor and filling a top opening of the deep trench and a second isolation portion directly contacting the first isolation potion and surrounding the deep trench without overlapping the deep trench. The thickness of the second isolation portion is larger than the thickness of the first isolation portion.
摘要翻译： DRAM的沟槽电容器的隔离结构具有覆盖沟槽电容器并填充深沟槽的顶部开口的第一隔离部分和与第一隔离部分直接接触并围绕深沟槽的第二隔离部分，而不与深沟槽重叠。第二隔离部分的厚度大于第一隔离部分的厚度。

4. 发明授权

US08486834B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08486834B2
公开(公告)日：2013-07-16
申请号：US13115039
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L27/10873 , H01L21/76834 , H01L21/7684 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
摘要翻译：本公开提供了一种用于制造存储器件的方法，包括：提供形成在衬底上的多个栅极结构，其中栅极结构包括设置在栅极结构的顶部上的覆盖层，并且每个两个相邻的栅极结构由一个沟; 在基底上覆盖地形成多晶硅层以填补间隙; 对多晶硅层进行平坦化处理，获得多晶硅插塞; 并且在平坦化处理之后进行氧化处理，将多晶硅插塞的一部分和栅极结构上的剩余多晶硅层转换成氧化硅。

5. 发明授权

US08399321B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08399321B2
公开(公告)日：2013-03-19
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

6. 发明授权

US07098049B2 Shallow trench isolation void detecting method and structure for the same 有权
标题翻译：浅沟隔离空洞检测方法和结构相同
公开(公告)号：US07098049B2
公开(公告)日：2006-08-29
申请号：US10714952
申请日：2003-11-18
申请人： Ping Hsu , Yi-Nan Chen
发明人： Ping Hsu , Yi-Nan Chen
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , G01R31/2884 , G11C29/006 , H01L21/76224
摘要： Disclosed is a method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.
摘要翻译：公开了一种用于检测半导体晶片的STI空隙的方法。本发明的方法包括以下步骤：在晶片的预定区域中分配检测区域; 通过与晶片的其它区域同步的工艺形成与有源区域交叉的有源区和栅极条。电介质材料填充在有源区域之间。有效区域之间的相邻部分至少达到预定长度。测量栅极条的电气值以确定在有源区域之间填充的电介质是否存在空隙，由此导出在晶片的其它区域的有源区域之间在STI中产生的任何空隙。

7. 发明申请

US20120302060A1 METHOD FOR MANUFACTURING MEMORY DEVICE 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120302060A1
公开(公告)日：2012-11-29
申请号：US13115039
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L27/10873 , H01L21/76834 , H01L21/7684 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
摘要翻译：本公开提供了一种用于制造存储器件的方法，包括：提供形成在衬底上的多个栅极结构，其中栅极结构包括设置在栅极结构的顶部上的覆盖层，并且每个两个相邻的栅极结构由一个沟; 在基底上覆盖地形成多晶硅层以填补间隙; 对多晶硅层进行平坦化处理，获得多晶硅插塞; 并且在平坦化处理之后进行氧化处理，将多晶硅插塞的一部分和栅极结构上的剩余多晶硅层转换成氧化硅。

8. 发明申请

US20120302049A1 METHOD FOR IMPLANTING WAFER 审中-公开
标题翻译：埋植方法
公开(公告)号：US20120302049A1
公开(公告)日：2012-11-29
申请号：US13115030
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/265
CPC分类号： H01L21/26513
摘要： The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different.
摘要翻译：本公开提供了一种用于晶片植入的方法，包括以下步骤：提供晶片，其中晶片包括中心圆形部分和与晶片边缘相邻的外围环形部分，并且其中中心圆形部分和周边环形部分是同心的以及将离子束注入到所述晶片中，其中所述中心圆形部分具有第一平均植入剂量，并且所述周边环形部分具有第二平均植入剂量，并且所述第一平均植入剂量和所述第二平均植入剂量是不同的。

9. 发明申请

US20120295408A1 METHOD FOR MANUFACTURING MEMORY DEVICE 有权
标题翻译：制造存储器件的方法
公开(公告)号：US20120295408A1
公开(公告)日：2012-11-22
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

10. 发明申请

US20050247930A1 Shallow trench isolation void detecting method and structure for the same 审中-公开
标题翻译：浅沟隔离空洞检测方法和结构相同
公开(公告)号：US20050247930A1
公开(公告)日：2005-11-10
申请号：US11179518
申请日：2005-07-13
申请人： Ping Hsu , Yi-Nan Chen
发明人： Ping Hsu , Yi-Nan Chen
IPC分类号： G01R31/28 , G11C29/00 , H01L21/762 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , G01R31/2884 , G11C29/006 , H01L21/76224
摘要： Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.
摘要翻译：披露的是检测半导体晶片的STI空隙的方法。本发明的方法包括以下步骤：在晶片的预定区域中分配检测区域; 通过与晶片的其它区域同步的工艺形成与有源区域交叉的有源区和栅极条。电介质材料填充在有源区域之间。有效区域之间的相邻部分至少达到预定长度。测量栅极条的电气值以确定在有源区域之间填充的电介质是否存在任何空隙，由此导出在晶片的其它区域的有源区域之间在STI中产生的任何空隙。

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