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1. 发明申请

US20050241672A1 Extraction of impurities in a semiconductor process with a supercritical fluid 审中-公开
标题翻译：用超临界流体萃取半导体工艺中的杂质
公开(公告)号：US20050241672A1
公开(公告)日：2005-11-03
申请号：US10917772
申请日：2004-08-13
申请人： Phillip Matz , Sameer Ajmera , Ju-Ai Ruan , Jinyoung Kim , Zhijian Lu , Laura Matz
发明人： Phillip Matz , Sameer Ajmera , Ju-Ai Ruan , Jinyoung Kim , Zhijian Lu , Laura Matz
IPC分类号： B08B6/00 , B08B7/00 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/3105 , B08B7/0021 , H01L21/02101
摘要： A method comprises extracting impurities from one or more materials in a semiconductor device via treatment with a supercritical fluid (SCF). The SCF may comprise a solvent and one or more co-solvents. Solvents may comprise 1-hexanol, 1-propanol, 2-propanol, acetone, ammonia, argon, carbon dioxide, chlorotrifluoromethane, cyclohexane, dichlorodifluoromethane, ethane, ethyl alcohol, ethylene, methane, methanol, n-butane, n-hexane, nitrous oxide, n-pentane, propane, propylene, toluene, trichlorofluoromethane, trichloromethane, water, or combinations thereof.
摘要翻译：一种方法包括通过用超临界流体（SCF）处理从半导体器件中的一种或多种材料中提取杂质。 SCF可以包含溶剂和一种或多种共溶剂。溶剂可以包括1-己醇，1-丙醇，2-丙醇，丙酮，氨，氩气，二氧化碳，三氟甲烷，环己烷，二氯二氟甲烷，乙烷，乙醇，乙烯，甲烷，甲醇，正丁烷，正己烷，亚硝酸氧化物，正戊烷，丙烷，丙烯，甲苯，三氯氟甲烷，三氯甲烷，水或其组合。

2. 发明申请

US20070080426A1 Single lithography-step planar metal-insulator-metal capacitor and resistor 审中-公开
标题翻译：单光刻阶平面金属 - 绝缘体 - 金属电容和电阻
公开(公告)号：US20070080426A1
公开(公告)日：2007-04-12
申请号：US11246249
申请日：2005-10-11
申请人： Phillip Matz , Sameer Ajmera , Darius Crenshaw
发明人： Phillip Matz , Sameer Ajmera , Darius Crenshaw
IPC分类号： H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： MIMCAP semiconductor devices and methods for fabrication MIMCAP semiconductor devices that include a grown capacitor dielectric are provided. Exemplary MIMCAP semiconductor devices can include a bottom electrode, a grown capacitor dielectric on the bottom electrode, and a top electrode on the capacitor dielectric. The grown layer can have a k-value greater than 1 and can be formed of, for example, an oxide or nitride that is chemically or thermally grown from the bottom electrode.
摘要翻译：提供MIMCAP半导体器件和用于制造包括生长电容器电介质的MIMCAP半导体器件的方法。示例性MIMCAP半导体器件可以包括底部电极，底部电极上生长的电容器电介质和电容器电介质上的顶部电极。生长层可以具有大于1的k值，并且可以由例如从底部电极化学或热生长的氧化物或氮化物形成。

3. 发明申请

US20060160299A1 Single mask MIM capacitor and resistor with in trench copper drift barrier 有权
标题翻译：单掩模MIM电容器和电阻器具有沟槽铜漂移屏障
公开(公告)号：US20060160299A1
公开(公告)日：2006-07-20
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Rao , Darius Crenshaw , Stephan Grunow , Kenneth Brennan , Somit Joshi , Montray Leavy , Phillip Matz , Sameer Ajmera , Yuri Solomentsev
发明人： Satyavolu Rao , Darius Crenshaw , Stephan Grunow , Kenneth Brennan , Somit Joshi , Montray Leavy , Phillip Matz , Sameer Ajmera , Yuri Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译：公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料，的铜/底电极的沉积。随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152）还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。

4. 发明申请

US20060024902A1 Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect 有权
标题翻译：金属绝缘体金属（MIM）电容器制造与侧壁屏障去除方面
公开(公告)号：US20060024902A1
公开(公告)日：2006-02-02
申请号：US10903712
申请日：2004-07-30
申请人： Sameer Ajmera , Darius Crenshaw , Stephan Grunow , Satyavolu Papa Rao , Phillip Matz
发明人： Sameer Ajmera , Darius Crenshaw , Stephan Grunow , Satyavolu Papa Rao , Phillip Matz
IPC分类号： H01L21/20
CPC分类号： H01L28/75
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).
摘要翻译：公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。一层底部电极/铜扩散阻挡材料（136）在其中限定电容器（100）的孔（128）内形成（16）。底部电极层（136）通过定向工艺形成，使得层（136）的水平方面（138）形成在孔（128）底部的金属（110）上至厚度（142）大于形成在孔（128）的侧壁（132）上的层（136）的侧壁方面（148）的厚度（144）。因此，在蚀刻行为（18）期间移除较薄的侧壁方面（148），而较厚的水平方面（138）中的一些保留。然后将一层电容器电介质材料（150）保形地形成（20）到孔128中并且在水平方面（138）上。然后在电容器介电材料（150）的层上共形形成（22）顶层电极材料层（152）以完成电容器堆叠（154）。

5. 发明申请

US20050233586A1 Method to reduce silanol and improve barrier properties in low K dielectric IC interconnects 有权
标题翻译：降低硅烷醇并改善低K介质IC互连中阻挡性能的方法
公开(公告)号：US20050233586A1
公开(公告)日：2005-10-20
申请号：US10901708
申请日：2004-07-27
申请人： Phillip Matz , Sameer Ajmera , Changming Jin , Trace Hurd
发明人： Phillip Matz , Sameer Ajmera , Changming Jin , Trace Hurd
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/44 , H01L21/768
CPC分类号： H01L21/02063 , H01L21/02052 , H01L21/3105 , H01L21/31058 , H01L21/31116 , H01L21/31138 , H01L21/7682
摘要： A trench and via structure is formed in a low k dielectric layer (100) formed over a silicon substrate (10). Super critical CO2 and a first silylization agent are used to form a chemically bonded high density surface layer (160). Silanol species are removed from the low k dielectric layer (100) using super critical CO2 and a second silylization agent. A barrier layer (190) and copper (200) are used to fill the trench and via structure.
摘要翻译：在形成在硅衬底（10）上的低k电介质层（100）中形成沟槽和通孔结构。超临界CO 2和第一甲硅烷基化剂用于形成化学键合的高密度表面层（160）。使用超临界CO 2和第二甲硅烷化剂从低k电介质层（100）除去硅烷醇物质。阻挡层（190）和铜（200）用于填充沟槽和通孔结构。

6. 发明申请

US20080146043A1 METHOD FOR MANUFACTURING AN ISOLATION STRUCTURE USING AN ENERGY BEAM TREATMENT 有权
标题翻译：使用能量束处理制造隔离结构的方法
公开(公告)号：US20080146043A1
公开(公告)日：2008-06-19
申请号：US11610758
申请日：2006-12-14
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/00
CPC分类号： H01L21/3105 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.
摘要翻译：本发明提供一种制造半导体器件的方法。用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

7. 发明授权

US07524777B2 Method for manufacturing an isolation structure using an energy beam treatment 有权
标题翻译：使用能量束处理制造隔离结构的方法
公开(公告)号：US07524777B2
公开(公告)日：2009-04-28
申请号：US11610758
申请日：2006-12-14
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/00
CPC分类号： H01L21/3105 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.
摘要翻译：本发明提供一种制造半导体器件的方法。用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

8. 发明申请

US20080076225A1 METHOD FOR MANUFACTURING A GATE SIDEWALL SPACER USING AN ENERGY BEAM TREATMENT 有权
标题翻译：使用能量束处理方法制造闸门间隔板的方法
公开(公告)号：US20080076225A1
公开(公告)日：2008-03-27
申请号：US11533798
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法可以包括在衬底上形成栅极结构，形成靠近栅极结构的侧壁的栅极侧壁间隔的至少一部分，以及使栅极侧壁间隔物的至少一部分能量束处理被配置为改变栅极侧壁间隔物的至少一部分的应力，从而改变其下的衬底中的应力。

9. 发明申请

US20070117371A1 Integration of pore sealing liner into dual-damascene methods and devices 有权
标题翻译：将密封衬垫整合到双镶嵌方法和装置中
公开(公告)号：US20070117371A1
公开(公告)日：2007-05-24
申请号：US11286877
申请日：2005-11-23
申请人： Edward Engbrecht , Satyavolu Rao , Sameer Ajmera , Stephan Grunow
发明人： Edward Engbrecht , Satyavolu Rao , Sameer Ajmera , Stephan Grunow
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76844
摘要： A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
摘要翻译：装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。包括金属互连的金属互连层形成在半导体本体上。介电层形成在金属互连层上。导电沟槽特征和导电通孔特征形成在电介质层中。孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。孔密封衬垫基本上不存在于导电通孔特征的底表面上。

10. 发明授权

US07465635B2 Method for manufacturing a gate sidewall spacer using an energy beam treatment 有权
标题翻译：使用能量束处理制造栅极侧壁间隔物的方法
公开(公告)号：US07465635B2
公开(公告)日：2008-12-16
申请号：US11533798
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法可以包括在衬底上形成栅极结构，形成靠近栅极结构的侧壁的栅极侧壁间隔的至少一部分，以及使栅极侧壁间隔物的至少一部分能量束处理被配置为改变栅极侧壁间隔物的至少一部分的应力，从而改变其下的衬底中的应力。

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