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1. 发明授权

US6031297A Printed circuit board allowing usage of alternative pin-compatible modules 失效
标题翻译：印刷电路板，允许使用替代引脚兼容模块
公开(公告)号：US6031297A
公开(公告)日：2000-02-29
申请号：US161931
申请日：1998-09-28
申请人： Philippe Louis , Michel Verhaeghe
发明人： Philippe Louis , Michel Verhaeghe
IPC分类号： H05K1/02 , H02J1/00
CPC分类号： H05K1/0233 , Y10T307/50 , Y10T307/696
摘要： Printed circuit board comprising two power supplies V.sub.1 and V.sub.2 and a ground (GND), and a plurality of modules among which at least one module supplied by one of the power supplies can be replaced by another pin-compatible module supplied by the other power supply, each power supply being supplied in each case by a circuit including a ferrite connected to the power supply and a capacitor connected to the ground in order to filter the high frequency signals due to the switching operations in the modules. The board comprises a first area (24 or 24') having a first and a second terminals which is dedicated to a first ferrite to be connected to one power supply by means of its first terminal, and a second area (26 or 26') having a first and a second terminals and being dedicated to a second ferrite to be connected to the other power supply by means of its first terminal, each area including a connecting means for connecting the second terminal associated with the area to the footprints of the module.
摘要翻译：包括两个电源V1和V2以及接地（GND）的印刷电路板，以及多个模块，其中由一个电源提供的至少一个模块可由另一电源供应的另一个引脚兼容模块代替在每种情况下，通过包括连接到电源的铁氧体的电路和连接到地的电容器来提供每个电源，以便由于模块中的切换操作而对高频信号进行滤波。所述板包括具有第一和第二端子的第一区域（24或24'），所述第一和第二端子专用于通过其第一端子连接到一个电源的第一铁氧体，以及第二区域（26或26'）具有第一和第二端子，并且专用于通过其第一端子连接到另一电源的第二铁氧体，每个区域包括用于将与该区域相关联的第二端子连接到模块的覆盖区的连接装置。

2. 发明授权

US06509811B2 Method for reducing the effects of signal reflections in a data communications network 失效
标题翻译：减少数据通信网络信号反射影响的方法
公开(公告)号：US06509811B2
公开(公告)日：2003-01-21
申请号：US09795643
申请日：2001-02-28
申请人： Philippe Klein , Claude Gomez , Michel Verhaeghe
发明人： Philippe Klein , Claude Gomez , Michel Verhaeghe
IPC分类号： H01P118
CPC分类号： G06F13/4086
摘要： A method for adjusting the signal transmission delay in a data transmission system wherein a driver transmits high speed data to a receiver through a plurality N of transmission media connected together. The link between the driver and the receiver is composed of a plurality of N traces, the length of the trace located on each transmission medium “i” being Li with “i” being an integer comprised between 1 and N. The method consists in adding to each trace of a transmission medium “i” a delay means generating a delay &Dgr;Ti equal to: Δ ⁢ ⁢ Ti = Ki · T0 2 - Li Vi with Ki being equal to n i N + 1 modulo 1, and wherein T0 is the minimum duration of a data pulse between its rising transition and its falling transition, ni is an integer equal to 1 or a number which is prime with N+1, and Vi is the propagation speed of the data signals in the trace “i”.
摘要翻译：一种用于调整数据传输系统中的信号传输延迟的方法，其中驱动器通过连接在一起的多个传输媒体向接收机发送高速数据。驱动器和接收器之间的链接由多条N条迹组成，位于每个传输介质“i”上的迹线的长度为Li，“i”为1和N之间的整数。该方法包括添加传输介质“i”的每个轨迹是产生等于1的延迟DELTATi的延迟装置，其中Ki等于1，其中T0是其上升转换和下降转换之间的数据脉冲的最小持续时间，ni是等于1的整数或N + 1的素数，Vi是跟踪“i”中数据信号的传播速度。

3. 发明授权

US06415363B1 Memory statistics counter and method for counting the number of accesses to a portion of memory 失效
标题翻译：存储器统计计数器和用于计数对存储器的一部分的访问次数的方法
公开(公告)号：US06415363B1
公开(公告)日：2002-07-02
申请号：US09512407
申请日：2000-02-24
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Michel Verhaeghe
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Michel Verhaeghe
IPC分类号： G06F1300
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/88
摘要： A memory statistic counter and method for counting the number of accesses (writes or reads) by a microprocessor (10) to at least a portion of a memory comprising a decoding logic unit (16) for providing a selection signal for selecting the portion of memory in response to control signals from the microprocessor, and adding logic units (18, 20, 22). The memory statistic counter includes a register which is incremented each time the portion of memory is accessed by the microprocessor and providing a registration signal when the number of accesses is equal to a predetermined number, and a queuing unit (44) for registering a value in a registering memory (50), such as a first-in-first-out (FIFO) memory, in response to the registration signal and providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined number of accesses to the portion of memory has occurred.
摘要翻译：一种存储器统计计数器和方法，用于将由微处理器（10）接收（写入或读取）的数量计数到包括解码逻辑单元（16）的存储器的至少一部分，用于提供用于选择存储器部分的选择信号响应于来自微处理器的控制信号，以及添加逻辑单元（18,20,22）。存储器统计计数器包括每当存储器部分被微处理器访问并且当访问次数等于预定数量时提供注册信号而递增的寄存器，以及用于将值存储在其中的排队单元（44）诸如先入先出（FIFO）存储器的登记存储器（50），其响应于所述注册信号，并且在所述注册存储器的所有位置已经被填充时向微处理器提供中断信号，由此指示对存储器部分的定义数量的访问已经发生的微处理器。

4. 发明授权

US4607139A Interface module for telephone lines 失效
标题翻译：电话线接口模块
公开(公告)号：US4607139A
公开(公告)日：1986-08-19
申请号：US618010
申请日：1984-06-06
申请人： Jean-Claude Froment , Jean-Pierre Pantani , Michel Verhaeghe
发明人： Jean-Claude Froment , Jean-Pierre Pantani , Michel Verhaeghe
IPC分类号： H04L29/10 , H03K5/02 , H04L5/14 , H04M11/06 , H04M11/00
CPC分类号： H04M11/06 , H03K5/02 , H04L5/143
摘要： A monolithic module acting as the interface between a modem and leased ("LL") or switched ("SL") telephone lines, mainly characterized in that: 1. It can be formed on a silicon chip (due to the absence of electromechanical relays or similar switching means), and 2. Its architecture is such that it makes it possible, by interconnecting or "stacking" identical modules, not only to attach additional telephone lines, but also to increase the number of allowable modem configurations. The module (10, 10') comprises two controlled-type line amplifiers (DLL, DSL) which exhibit a high output impedance regardless of whether the power supplies are "on" or "off"; two controlled-type line receivers (RSL, RLL) which provide a very high input impedance whether the power supplies are "on" or "off"; and a wrap receiver (WRP) for testing the modem (to the exclusion of the telephone lines) and interconnecting or "stacking" identical modules. The figure shows an embodiment wherein two of the modules are interconnected; various configurations can be obtained depending on the logic state of the control inputs (1 to 4 for module 10 and 1' to 4' for module 10') supplied by the modem.
摘要翻译：作为调制解调器和租用（“LL”）或交换（“SL”）电话线路之间的接口的单片模块，其主要特征在于：1.它可以形成在硅芯片上（由于没有机电继电器或类似的切换装置）和2.其架构使得它可以通过互连或“堆叠”相同的模块，不仅可以附加附加的电话线，而且可以增加允许的调制解调器配置的数量。模块（10,10'）包括两个受控类型的线路放大器（DLL，DSL），其表现出高的输出阻抗，而不管电源是“开”还是“关”。两个控制型线路接收器（RSL，RLL），无论电源是“开”还是“关”，都提供非常高的输入阻抗; 以及用于测试调制解调器（排除电话线）和互连或“堆叠”相同模块的包裹接收器（WRP）。该图示出了其中两个模块互连的实施例; 取决于调制解调器提供的控制输入（模块10的1到4和模块10'的1'到4'）的逻辑状态可以获得各种配置。

5. 发明授权

US06789130B1 Automatic rate adaptation system in a local area network 失效
标题翻译：局域网自动速率调整系统
公开(公告)号：US06789130B1
公开(公告)日：2004-09-07
申请号：US09571681
申请日：2000-05-16
申请人： Alain Benayoun , Jean-Francois Le Pennec , Michel Verhaeghe , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Michel Verhaeghe , Patrick Michel
IPC分类号： G06F1516
CPC分类号： H04L12/5602
摘要： Automatic speed adaptation system in a Local Area Network (LAN) between a hub (10) including a hub adapter (20, 24, 28) and at least a workstation (12, 14, 16) including a workstation adapter (18, 22, 26) for exchanging data over a link connected between the hub adapter and the workstation adapter at a rate based on a frequency which is inversely proportional to the length of the link. Each adapter comprises a clock generator for generating a clock having a frequency between F1 and F2 and processing means for transmitting at least a check frame from the hub adapter to the workstation adapter at a rate based on a frequency VCLK generated by the clock generator under the control of the processing means and selected as being the frequency corresponding to the length of the link, and for transmitting an acknowledge frame from the workstation adapter to the hub adapter thereby ascertaining that the selected frequency is the right frequency resulting in the best quality of transmission.
摘要翻译：在包括轮毂适配器（20,24,28）的轮毂（10）和至少包括工作站适配器（18,22）的工作站（12,14,16）之间的局域网（LAN）中的自动速度适配系统， 26），用于以基于与链路的长度成反比的频率的速率通过连接在中继适配器和工作站适配器之间的链路交换数据。每个适配器包括用于产生具有F1和F2之间的频率的时钟的时钟发生器和用于以基于由时钟发生器下的时钟发生器产生的频率VCLK的速率从集线器适配器至工作站适配器发送至少一个校验帧的处理装置处理装置的控制并被选择为对应于链路的长度的频率，并且用于将确认帧从工作站适配器发送到集线器适配器，从而确定所选择的频率是合适的频率，从而产生最佳传输质量。

6. 发明授权

US06384622B2 Device for cancelling the reflection effects between a driver and a plurality of receivers 失效
标题翻译：用于消除驱动器和多个接收器之间的反射效应的装置
公开(公告)号：US06384622B2
公开(公告)日：2002-05-07
申请号：US09795628
申请日：2001-02-28
申请人： Michel Verhaeghe , Christian Ouazana , Patrick Michel , Bernard Sergent
发明人： Michel Verhaeghe , Christian Ouazana , Patrick Michel , Bernard Sergent
IPC分类号： H03K1716
CPC分类号： H04L25/10 , H04L25/0278 , H04L25/03878
摘要： Device for cancelling the effects of the reflection in a signal transmission system (10) including a driver (12) and a plurality of n receivers (14, 16) wherein signals are sent according to a multipoint topology from the driver to the receivers, each receiver having an internal capacitance and sending back reflection signals to the driver each time a signal is transmitted thereto by the driver. The device comprises circuit means causing the signal resulting from the sequential reflections due to a given receiver and then due to the driver to have the same magnitude but the reverse sign as the sum of all signals received in the given receiver resulting from the reflections due to all receivers, and the net linking the driver to each receiver comprises delay means (40) enabling the propagating time of a signal sent from the driver to this receiver to be identical for each receiver, whereby the total sum of all reflection signals arriving in the given receiver at the same time is equal to zero.
摘要翻译：用于消除包括驱动器（12）和多个n个接收器（14,16）的信号传输系统（10）中的反射效应的装置，其中根据从驾驶员到接收机的多点拓扑发送信号，每个接收机具有内部电容，并且每次当驾驶员向其发送信号时，将反射信号发送给驾驶员。该装置包括电路装置，使得由于给定的接收机而产生的连续反射产生的信号，然后由于驱动器具有相同的幅度，而是与给定接收机中接收到的所有信号的总和相反的结果，这是由于由于所有接收器和将驱动器链接到每个接收器的网络包括延迟装置（40），使得从驾驶员向该接收机发送的信号的传播时间对于每个接收机是相同的，由此到达所有接收机的所有反射信号的总和给定的接收机同时等于零。

7. 发明授权

US4918448A Device for extending the resolution of a N-bit resistive digital-to-analog converter to a (N+P)-bit digital-to-analog converter 失效
标题翻译：用于将N位电阻数模转换器的分辨率扩展到（N + P）位数模转换器的装置
公开(公告)号：US4918448A
公开(公告)日：1990-04-17
申请号：US249542
申请日：1988-09-26
申请人： Philippe Hauviller , Michel Verhaeghe
发明人： Philippe Hauviller , Michel Verhaeghe
IPC分类号： H03M1/70 , H03M1/00 , H03M1/68
CPC分类号： H03M1/661 , H03M1/682 , H03M1/765
摘要： A device implemented in a N-bit digital-to-analog converter (DAC) to extend its resolution to N+P bits. The N-bit DAC comprises a resistive string 2 made of 2.sup.N resistive elements R1 to R16. MSB switches in block 10 and LSB switches in block 12, when closed in response to combinations of the N-bits provide the voltage at one of taps N1 to N16 to node M1. The device comprises a string 18 made of 2.sup.P-2 elements connected between nodes M1 and M7, additional LSB switch block 14 and additional MSB switches SW4-2, SW8-2, SW12-2 and SW16-2 which are closed in response to combinations of the N-bits to connect the string 18 across the taps of a selected resistor R1 to R16. The voltage generated at one of the taps M1 to M7 of string 18 is provided to the (N+P)-bit DAC output 20 by means of one of the switches in block 16. The main advantages of this device are that the monotonicity of the conversion is not impaired by the extension to (N+P) bits, and that it is not space consuming when integrated in a chip. Furthermore, various conversion capabilities may be provided by controlling the switch SW21 and the switches in block 16.

8. 发明授权

US06239985B1 High speed signals distribution for backplanes 失效
标题翻译：背板高速信号分配
公开(公告)号：US06239985B1
公开(公告)日：2001-05-29
申请号：US09385949
申请日：1999-08-30
申请人： Jacques Feraud , Michel Verhaeghe
发明人： Jacques Feraud , Michel Verhaeghe
IPC分类号： H05K114
CPC分类号： H05K1/0248 , H05K7/1459 , H05K2201/044 , H05K2201/09236 , H05K2201/09254 , H05K2201/09263
摘要： A method and apparatus for distribution of electrical signals in a circuit board. Specifically, the circuit board comprises a printed circuit board and a plurality of connectors attached to the circuit board for receiving components such as logic cards which each require a clock input. Each of the connectors may have a plurality of pins. A plurality of electrical conductors associated with the circuit board electrically couple a corresponding pin for a clock input from each connector to a common point by individual one of the plurality of electrical conductors. Each of the plurality of electrical conductors are so arranged that to have approximately the same length.
摘要翻译：一种用于在电路板中分配电信号的方法和装置。具体地，电路板包括印刷电路板和附接到电路板的多个连接器，用于接收各自需要时钟输入的逻辑卡的组件。每个连接器可以具有多个销。与电路板相关联的多个电导体将多个电导体中的一个电连接到相应的引脚以将来自每个连接器的时钟输入电耦合到公共点。多个电导体中的每一个被布置成具有大致相同的长度。

9. 发明授权

US4446385A Voltage comparator with a wide common mode input voltage range 失效
标题翻译：具有宽共模输入电压范围的电压比较器
公开(公告)号：US4446385A
公开(公告)日：1984-05-01
申请号：US327865
申请日：1981-12-07
申请人： Gerard Orengo , Michel Verhaeghe
发明人： Gerard Orengo , Michel Verhaeghe
IPC分类号： G01R19/165 , H03F3/45 , H03K5/08 , H03K5/24
CPC分类号： H03K5/2418 , H03F3/4508 , H03F3/45484
摘要： A voltage comparator circuit with a wide common mode input voltage range which extends beyond supply voltage parameter values. The comparator circuit utilizes an input stage having two input transistors, the emitter electrodes of which are connected to receive input signals and the collector electrodes of which are connected to two current sources. A current fixing circuit is coupled to the collector electrodes of said two input transistors and acts to fix the direct current in the collector circuits at a first value IO and the currents supplied by the current sources at a second value k IO, where k is greater than 2. An output stage is provided with two input circuits respectively connected to the collector electrodes of the two input transistors and with a logic circuit arrangement set to either one of two logic levels in accordance with the sign of the difference in the voltages applied to the pair of emitter electrodes of the two input transistors.
摘要翻译：具有宽泛共模输入电压范围的电压比较器电路，其延伸超出电源电压参数值。比较器电路使用具有两个输入晶体管的输入级，其输入电极连接以接收输入信号，并且其集电极连接到两个电流源。电流固定电路耦合到所述两个输入晶体管的集电极，用于将集电极电路中的直流电流固定在第一值IO和电流源提供的电流为第二值k IO，其中k大于输出级设置有分别连接到两个输入晶体管的集电极的两个输入电路，并且逻辑电路装置根据施加到...的电压差的符号设置为两个逻辑电平中的任一个两个输入晶体管的一对发射极。

10. 发明授权

US4412335A Digital signal distribution system 失效
标题翻译：数字信号分配系统
公开(公告)号：US4412335A
公开(公告)日：1983-10-25
申请号：US305564
申请日：1981-09-25
申请人： Jean-Claude Froment , Jean-Louis Marijon , Gerard Orengo , Michel Verhaeghe
发明人： Jean-Claude Froment , Jean-Louis Marijon , Gerard Orengo , Michel Verhaeghe
IPC分类号： H03K5/04 , G06F1/10 , H03K5/1252 , H04L7/00 , H04L7/04 , H04L25/20 , H04L25/40 , H04L25/52 , H03K6/02
CPC分类号： H03K5/1252 , H04L25/20 , H04L7/00
摘要： A digital signal distribution system for distributing digital signals to remote points of a machine. It is comprised of a distribution device arranged at each of said points. In each device, a receiver receives on its true and complementary inputs, the signal to be distributed. The drivers are connected to the receivers through a crossed connection, the true output of the receiver being connected to the complementary input of the driver, and the complementary output of the receiver being connected to the true input of the driver, so as to cancel the skew of the pulse width of the signal to be distributed. The signals on outputs of the driver circuits can be utilized locally or transmitted to another remote point.
摘要翻译：一种用于将数字信号分配到机器的远程点的数字信号分配系统。它由布置在每个所述点上的分配装置组成。在每个设备中，接收机接收其真实和互补的输入信号，以分配信号。驱动器通过交叉连接连接到接收器，接收器的真实输出连接到驱动器的互补输入，并且接收器的互补输出连接到驱动器的真实输入，以便取消要分配的信号的脉冲宽度偏移。驱动器电路的输出信号可以在本地使用或传输到另一个远程点。

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