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1. 发明授权

US06239985B1 High speed signals distribution for backplanes 失效
标题翻译：背板高速信号分配
公开(公告)号：US06239985B1
公开(公告)日：2001-05-29
申请号：US09385949
申请日：1999-08-30
申请人： Jacques Feraud , Michel Verhaeghe
发明人： Jacques Feraud , Michel Verhaeghe
IPC分类号： H05K114
CPC分类号： H05K1/0248 , H05K7/1459 , H05K2201/044 , H05K2201/09236 , H05K2201/09254 , H05K2201/09263
摘要： A method and apparatus for distribution of electrical signals in a circuit board. Specifically, the circuit board comprises a printed circuit board and a plurality of connectors attached to the circuit board for receiving components such as logic cards which each require a clock input. Each of the connectors may have a plurality of pins. A plurality of electrical conductors associated with the circuit board electrically couple a corresponding pin for a clock input from each connector to a common point by individual one of the plurality of electrical conductors. Each of the plurality of electrical conductors are so arranged that to have approximately the same length.
摘要翻译：一种用于在电路板中分配电信号的方法和装置。具体地，电路板包括印刷电路板和附接到电路板的多个连接器，用于接收各自需要时钟输入的逻辑卡的组件。每个连接器可以具有多个销。与电路板相关联的多个电导体将多个电导体中的一个电连接到相应的引脚以将来自每个连接器的时钟输入电耦合到公共点。多个电导体中的每一个被布置成具有大致相同的长度。

2. 发明授权

US5197065A Distribution mechanism for establishing communications between user interfaces of a communication system 失效
标题翻译：用于在通信系统的用户界面之间建立通信的分发机制
公开(公告)号：US5197065A
公开(公告)日：1993-03-23
申请号：US576876
申请日：1990-09-04
申请人： Jean Calvignac , Jacques Feraud , Jean-Pierre Lips , Bernard Naudin , Eric Saint-George
发明人： Jean Calvignac , Jacques Feraud , Jean-Pierre Lips , Bernard Naudin , Eric Saint-George
IPC分类号： H04L5/22 , H04L29/06 , H04Q11/04
CPC分类号： H04Q11/04
摘要： A distribution mechanism includes a scheduling device which partitions a common timing signal with a period T into n slots of t duration each, a configuration table having n addressable locations with each of the n locations storing communication control information and addressable by slot numbers generated by the scheduling device and a distribution buffer device (2) having at least a first and a second part, with each part having n addressable locations addressed by control information provided by the configuration table during each slot period to cause an interface involved in the to be established communications during a selected slot period, to write the information to be transmitted in one part of the distribution buffer and the information to be received by the interface to be read from the other part of the distribution buffer at addresses derived from the communication control information and the slot generated by the schedule means.
摘要翻译：分配机构包括：将具有周期T的公共定时信号分割为n个时隙的调度设备，每个n个时隙分别为n个时隙，具有n个可寻址位置，其中n个位置中的每一个存储通信控制信息，并且可由第调度设备和具有至少第一和第二部分的分发缓冲器设备（2），其中每个部分具有由每个时隙周期期间由配置表提供的控制信息寻址的n个可寻址位置，以引起所涉及的接口的建立在所选择的时隙期间进行通信，以从通信控制信息导出的地址将要发送的信息写入分发缓冲器的一部分中的信息和要从分发缓冲器的其他部分读取的接口的信息，以及由计划生成的时隙意味着。

3. 发明授权

US06670559B2 Electromagnetic shield for printed circuit boards 失效
公开(公告)号：US06670559B2
公开(公告)日：2003-12-30
申请号：US10016426
申请日：2001-12-10
申请人： Bruno Centola , Claude Gomez , Patrick Michel , Jacques Feraud
发明人： Bruno Centola , Claude Gomez , Patrick Michel , Jacques Feraud
IPC分类号： H01R1204
CPC分类号： H05K9/0039
摘要： An electromagnetic shield device for printed circuit boards (PCBs) which, in one embodiment, is made of conductive material and comprised of two parts. In another embodiment, the device is a singular element. In both examples, press-fit or compliant pins may be used to electrically couple the device to the PCB's ground layer. Alternatively, projecting pins or flat conductive plates can be used to provide this coupling. The device is also adjustable to accommodate PCBs of varying thicknesses. The device provides for added PCB stiffness while assuring prevention of electromagnetic radiation from the PCB's edge.

4. 发明授权

US5119478A Parallel processing method and device for receiving and transmitting HDLC SDLC bit streams 失效
标题翻译：并行处理方法和接收和发送HDLC SDLC位流的设备
公开(公告)号：US5119478A
公开(公告)日：1992-06-02
申请号：US357225
申请日：1989-05-26
申请人： Jean Calvignac , Jacques Feraud , Bernard Naudin , Claude Pin , Eric Saint-Georges
发明人： Jean Calvignac , Jacques Feraud , Bernard Naudin , Claude Pin , Eric Saint-Georges
IPC分类号： H04L29/02 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , H04L69/12 , H04L69/324
摘要： The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N

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