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1. 发明授权

US06410399B1 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization 失效
标题翻译：通过硅化法降低基于沟槽的DRAMS中的带，字线和位线接触电阻的工艺
公开(公告)号：US06410399B1
公开(公告)日：2002-06-25
申请号：US09606493
申请日：2000-06-29
申请人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
发明人： Philip Lee Flaitz , Herbert L. Ho , Subramanian Iyer , Babar Khan , Paul C. Parries
IPC分类号： H01L2120
CPC分类号： H01L27/10867 , H01L21/28052 , H01L21/28518 , H01L21/76895 , H01L29/665
摘要： A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.
摘要翻译：一种半导体器件制造方法，用于在动态随机存取存储器（DRAMS）和嵌入式DRAM（eDRAM）器件的阵列区域中硅化硅含量区域，以降低电阻，并在低温下提高器件的可靠性。

2. 发明授权

US06429101B1 Method of forming thermally stable polycrystal to single crystal electrical contact structure 失效
标题翻译：将热稳定多晶体形成为单晶电接触结构的方法
公开(公告)号：US06429101B1
公开(公告)日：2002-08-06
申请号：US09240753
申请日：1999-01-29
申请人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
发明人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
IPC分类号： H01L2120
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02236 , H01L21/02249 , H01L21/02255 , H01L21/31662
摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.
摘要翻译：一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

3. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

4. 发明授权

US07791124B2 SOI deep trench capacitor employing a non-conformal inner spacer 失效
标题翻译： SOI深沟槽电容器采用非保形内隔板
公开(公告)号：US07791124B2
公开(公告)日：2010-09-07
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

5. 发明授权

US07705386B2 Providing isolation for wordline passing over deep trench capacitor 有权
标题翻译：提供字沟通过深沟槽电容器的隔离
公开(公告)号：US07705386B2
公开(公告)日：2010-04-27
申请号：US11969989
申请日：2008-01-07
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
IPC分类号： H01L27/108 , H01L21/8244
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译：存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。衬垫可以是一层氧化物上的氮化物层。一些STI可以覆盖衬垫的一部分。在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

6. 发明申请

US20090289291A1 SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER 失效
标题翻译： SOI深层电容器采用不合格的内部间隔器
公开(公告)号：US20090289291A1
公开(公告)日：2009-11-26
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

7. 发明申请

US20110092043A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20110092043A1
公开(公告)日：2011-04-21
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

8. 发明申请

US20090184356A1 DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP 有权
标题翻译：在具有横向延伸的带状纹的SOI衬底中的深度TRENCH电容器
公开(公告)号：US20090184356A1
公开(公告)日：2009-07-23
申请号：US12016312
申请日：2008-01-18
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

9. 发明申请

US20090173980A1 PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR 有权
标题翻译：提供隔离通过深度电容电容器进行字线传输
公开(公告)号：US20090173980A1
公开(公告)日：2009-07-09
申请号：US11969989
申请日：2008-01-07
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Herbert L. Ho , Paul C. Parries
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10891
摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
摘要翻译：存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。衬垫可以是一层氧化物上的氮化物层。一些STI可以覆盖衬垫的一部分。在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

10. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

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