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1. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

2. 发明申请

US20110180862A1 EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
标题翻译：嵌入式动态随机访问存储器件和方法
公开(公告)号：US20110180862A1
公开(公告)日：2011-07-28
申请号：US12692760
申请日：2010-01-25
申请人： Brent A. Anderson , John E. Barth, JR. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
发明人： Brent A. Anderson , John E. Barth, JR. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
IPC分类号： H01L27/12 , H01L27/108 , H01L21/8242
CPC分类号： H01L21/84 , H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
摘要翻译：本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法晶圆。本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

3. 发明授权

US09059319B2 Embedded dynamic random access memory device and method 有权
标题翻译：嵌入式动态随机存取存储器件及方法
公开(公告)号：US09059319B2
公开(公告)日：2015-06-16
申请号：US12692760
申请日：2010-01-25
申请人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
发明人： Brent A. Anderson , John E. Barth, Jr. , Herbert L. Ho , Edward J. Nowak , Wayne Trickle
IPC分类号： H01L27/108 , H01L21/84 , H01L29/66
CPC分类号： H01L21/84 , H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.
摘要翻译：本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法晶圆。本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

4. 发明授权

US08492819B2 FET eDRAM trench self-aligned to buried strap 失效
标题翻译： FET eDRAM沟槽自对准到掩埋带
公开(公告)号：US08492819B2
公开(公告)日：2013-07-23
申请号：US13182738
申请日：2011-07-14
申请人： Brent A. Anderson , John E. Barth, Jr. , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John E. Barth, Jr. , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/06 , H01L21/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087
摘要： A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
摘要翻译：一种制造场效应晶体管（FET）嵌入式动态随机存取存储器（eDRAM）单元阵列的结构和方法，其包括：延伸到绝缘体上硅（SOI）的掩埋氧化物（BOX）层的掩埋硅带，基质; 向下延伸到SOI衬底的衬底层的凹陷沟槽电容器; 形成在所述凹槽沟槽电容器上的导电顶板的与所述掩埋硅带的第一侧表面接触的侧表面; 设置在导电顶板上方的电介质盖; 由所述SOI衬底的硅层形成的第一FET，其中所述第一FET的源极/漏极区域接触所述埋入硅带的第二侧表面; 以及经过的字线，设置在电介质盖的与埋置硅带相对并分离并连接到FET eDRAM单元阵列的相邻行中的第二FET的栅极的部分上。

5. 发明申请

US20130015515A1 FET eDRAM TRENCH SELF-ALIGNED TO BURIED STRAP 失效
标题翻译： FET eDRAM TRENCH自对准到BURIED STRAP
公开(公告)号：US20130015515A1
公开(公告)日：2013-01-17
申请号：US13182738
申请日：2011-07-14
申请人： Brent A. Anderson , John E. Barth, JR. , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John E. Barth, JR. , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/8242 , H01L27/06
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087
摘要： A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.
摘要翻译：一种制造场效应晶体管（FET）嵌入式动态随机存取存储器（eDRAM）单元阵列的结构和方法，其包括：延伸到绝缘体上硅（SOI）的掩埋氧化物（BOX）层的掩埋硅带，基质; 向下延伸到SOI衬底的衬底层的凹陷沟槽电容器; 形成在所述凹槽沟槽电容器上的导电顶板的与所述掩埋硅带的第一侧表面接触的侧表面; 设置在导电顶板上方的电介质盖; 由所述SOI衬底的硅层形成的第一FET，其中所述第一FET的源极/漏极区域接触所述埋入硅带的第二侧表面; 以及经过的字线，设置在电介质盖的与埋置硅带相对并分离并连接到FET eDRAM单元阵列的相邻行中的第二FET的栅极的部分上。

6. 发明授权

US06962838B2 High mobility transistors in SOI and method for forming 失效
标题翻译： SOI中的高迁移率晶体管和形成方法
公开(公告)号：US06962838B2
公开(公告)日：2005-11-08
申请号：US10447579
申请日：2003-05-29
申请人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/84 , H01L27/12 , H01L21/00
CPC分类号： H01L29/7842 , H01L21/84 , H01L27/1203
摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.
摘要翻译：本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。通过对硅岛施加物理应变来增加空穴迁移率。通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

7. 发明授权

US06624478B2 High mobility transistors in SOI and method for forming 有权
标题翻译： SOI中的高迁移率晶体管和形成方法
公开(公告)号：US06624478B2
公开(公告)日：2003-09-23
申请号：US09683656
申请日：2002-01-30
申请人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Xavier Baie , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L29/7842 , H01L21/84 , H01L27/1203
摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.
摘要翻译：本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。通过对硅岛施加物理应变来增加空穴迁移率。通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

8. 发明授权

US08193067B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08193067B2
公开(公告)日：2012-06-05
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L21/20
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

9. 发明申请

US20110133310A1 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT 有权
标题翻译：集成电路和使用集成工艺步骤形成集成电路的深层隔离分离结构和深层电容电容器结构的方法
公开(公告)号：US20110133310A1
公开(公告)日：2011-06-09
申请号：US12630091
申请日：2009-12-03
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/92 , H01L21/8242
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

10. 发明授权

US08492820B2 Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit 有权
标题翻译：集成电路和采用集成工艺步骤形成集成电路的深沟槽隔离结构和深沟槽电容器结构的方法
公开(公告)号：US08492820B2
公开(公告)日：2013-07-23
申请号：US13406664
申请日：2012-02-28
申请人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Herbert L. Ho , Edward J. Nowak
IPC分类号： H01L29/94
CPC分类号： H01L21/76224 , H01L27/10829 , H01L27/10867 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).
摘要翻译：公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

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