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1. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

2. 发明申请

US20080166857A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20080166857A1
公开(公告)日：2008-07-10
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

3. 发明授权

US08563398B2 Electrically conductive path forming below barrier oxide layer and integrated circuit 有权
标题翻译：阻挡氧化层下方的导电路径和集成电路
公开(公告)号：US08563398B2
公开(公告)日：2013-10-22
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

4. 发明授权

US07923840B2 Electrically conductive path forming below barrier oxide layer and integrated circuit 有权
标题翻译：阻挡氧化层下方的导电路径和集成电路
公开(公告)号：US07923840B2
公开(公告)日：2011-04-12
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L23/48
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

5. 发明申请

US20110092056A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20110092056A1
公开(公告)日：2011-04-21
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/762 , H01L21/3205
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

6. 发明授权

US5453400A Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits 失效
标题翻译：用于在集成电路的半导体衬底上互连不同多晶硅区的方法和结构
公开(公告)号：US5453400A
公开(公告)日：1995-09-26
申请号：US6662
申请日：1993-01-19
申请人： John R. Abernathey , Randy W. Mann , Paul C. Parries , Julie A. Springer
发明人： John R. Abernathey , Randy W. Mann , Paul C. Parries , Julie A. Springer
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/768 , H01L21/76895 , H01L23/53271 , H01L2924/0002
摘要： A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.
摘要翻译：提供了形成集成电路器件的互连的方法，特别是互连间隔开的源极/漏极区域和/或栅极区域以及所得到的结构。诸如二氧化硅的蚀刻停止材料沉积在其上形成器件的整个衬底上。一层硅沉积在蚀刻停止材料上，并且硅被选择性地蚀刻以在要连接的区域上露出蚀刻停止材料。然后去除那些区域处的蚀刻停止材料。此后，在连接间隔开的区域的基板上形成高导电性材料，其是由硅层和难熔金属形成的难熔金属或硅化物。

7. 发明授权

US07466604B2 SRAM voltage control for improved operational margins 有权
标题翻译： SRAM电压控制，提高运营利润率
公开(公告)号：US07466604B2
公开(公告)日：2008-12-16
申请号：US11998948
申请日：2007-12-03
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.
摘要翻译：提供了一种静态随机存取存储器（“SRAM”），其包括以具有多个部分的阵列布置的多个SRAM单元。 SRAM包括对应于阵列的多个部分中的相应部分的多个电压控制电路。多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于多个所选择的多个SRAM单元中的多个SRAM单元的电源输入的电压的功能的SRAM部分。在将位写入属于所选部分的SRAM单元之一的写操作期间，所选部分的电源电压降低。

8. 发明授权

US07313032B2 SRAM voltage control for improved operational margins 有权
标题翻译： SRAM电压控制，提高运营利润率
公开(公告)号：US07313032B2
公开(公告)日：2007-12-25
申请号：US11164556
申请日：2005-11-29
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G11C5/14 , G11C11/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
摘要翻译：提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

9. 发明授权

US08099688B2 Circuit design 有权
标题翻译：电路设计
公开(公告)号：US08099688B2
公开(公告)日：2012-01-17
申请号：US11985961
申请日：2007-11-19
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G06F17/50
CPC分类号： G11C11/413 , G11C5/14
摘要： A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and logic gates, and is stored in the non-transitory computer-readable medium. When executed by the computer, the netlist produces the circuit design. The circuit design comprises a static random access memory (“SRAM”) including a plurality of SRAM cells arranged in an array, including a plurality of rows and a plurality of columns, and a plurality of column voltage control circuits corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply and is operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of the plurality of columns. The selected column is selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected column. Each column voltage control circuit includes an NFET and a pair of PFETs. Each NFET and pair of PFETs has a conduction path directly connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.
摘要翻译：设计过程包括输入表示在非暂时计算机可读介质中体现的电路设计的设计文件，并使用计算机将电路设计转换成网表。网表包括多个线，晶体管和逻辑门的表示，并且存储在非暂时计算机可读介质中。当由计算机执行时，网表产生电路设计。该电路设计包括一个静态随机存取存储器（“SRAM”），它包括多个排列成阵列的SRAM单元，包括多行和多列，以及多个列电压控制电路，阵列的多列。多个电压控制电路中的每一个耦合到电源的输出，并且可操作以在到达时临时减小提供给属于所选择的列的所选列的多个SRAM单元的电源输入的位选择信号多列。在写入操作期间选择所选列，其中将位写入属于所选列的多个SRAM单元之一。每列电压控制电路包括NFET和一对PFET。每个NFET和一对PFET具有直接连接在电源的输出端与多个SRAM单元的电源输入端之间的导通路径。

10. 发明申请

US20090129191A1 Structure for SRAM voltage control for improved operational margins 有权
标题翻译： SRAM电压控制的结构，可提高操作裕度
公开(公告)号：US20090129191A1
公开(公告)日：2009-05-21
申请号：US11985961
申请日：2007-11-19
申请人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
发明人： Wayne F. Ellis , Randy W. Mann , David J. Wager , Robert C. Wong
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/14
摘要： A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns of the array, each coupled to an output of a power supply. Each voltage control circuit temporarily reduces a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The power supply voltage to the selected column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
摘要翻译：提供了包括静态随机存取存储器（“SRAM”）的设计结构，其包括以阵列布置的多个SRAM单元。阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的电压控制电路，每个耦合到电源的输出端。每个电压控制电路暂时降低提供给属于SRAM的选定列列的多个SRAM单元的电源输入的电压。在将位写入属于所选列的SRAM单元之一的写操作期间，对所选列的电源电压降低。

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