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1. 发明授权

US08445320B2 Graphene channel-based devices and methods for fabrication thereof 有权
标题翻译：石墨烯基通道器件及其制造方法
公开(公告)号：US08445320B2
公开(公告)日：2013-05-21
申请号：US12783676
申请日：2010-05-20
申请人： Phaedon Avouris , Kuan-Neng Chen , Damon Farmer , Yu-Ming Lin
发明人： Phaedon Avouris , Kuan-Neng Chen , Damon Farmer , Yu-Ming Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/50 , B82Y10/00 , B82Y40/00 , H01L21/8221 , H01L27/0688 , H01L27/092 , H01L27/1207 , H01L29/1606 , H01L29/66742 , H01L29/775 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
摘要翻译：提供了基于石墨烯基通道的器件及其制造技术。在一个方面，一种半导体器件包括：第一晶片，其具有形成在第一衬底上的至少一个石墨烯通道;围绕石墨烯通道的第一氧化物层;延伸穿过第一氧化物层的石墨烯通道的源极和漏极接触; 以及第二晶片，其具有形成在第二基板中的CMOS器件层，围绕所述CMOS器件层的第二氧化物层和延伸穿过所述第二氧化物层的所述CMOS器件层的多个触点，所述晶片通过氧化物层之间的氧化物 - 氧化物键。与CMOS器件层的一个或多个触点与源极和漏极触点接触。 CMOS器件层的一个或多个其它触点是用于石墨烯通道的栅极触点。

2. 发明授权

US08455297B1 Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology 有权
标题翻译：通过三维集成技术制造高性能碳纳米管晶体管集成电路的方法
公开(公告)号：US08455297B1
公开(公告)日：2013-06-04
申请号：US12831656
申请日：2010-07-07
申请人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
发明人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
IPC分类号： H01L51/40
CPC分类号： H01L21/768 , B82Y10/00 , B82Y40/00 , H01L21/50 , H01L21/6835 , H01L21/76885 , H01L23/4827 , H01L2221/1094 , H01L2221/68359 , H01L2224/83894 , H01L2924/01025 , H01L2924/01029 , H01L2924/01046
摘要： Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.
摘要翻译：提供了制造基于碳纳米管的器件的技术。一方面，提供一种制造碳纳米管集成电路的方法。该方法包括以下步骤。提供了包括碳纳米管的第一晶片。提供包括一个或多个器件元件的第二晶片。一个或多个碳纳米管通过将第一晶片和第二晶片结合在一起而与一个或多个器件元件连接。还提供了一种基于碳纳米管的集成电路。

3. 发明申请

US20130119548A1 METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY 有权
标题翻译：通过三维集成技术制造高性能碳纳米管晶体管集成电路的方法
公开(公告)号：US20130119548A1
公开(公告)日：2013-05-16
申请号：US12831656
申请日：2010-07-07
申请人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
发明人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
IPC分类号： H01L21/768 , H01L23/482 , H01L21/50
CPC分类号： H01L21/768 , B82Y10/00 , B82Y40/00 , H01L21/50 , H01L21/6835 , H01L21/76885 , H01L23/4827 , H01L2221/1094 , H01L2221/68359 , H01L2224/83894 , H01L2924/01025 , H01L2924/01029 , H01L2924/01046
摘要： Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.
摘要翻译：提供了制造基于碳纳米管的器件的技术。一方面，提供一种制造碳纳米管集成电路的方法。该方法包括以下步骤。提供了包括碳纳米管的第一晶片。提供包括一个或多个器件元件的第二晶片。一个或多个碳纳米管通过将第一晶片和第二晶片结合在一起而与一个或多个器件元件连接。还提供了一种基于碳纳米管的集成电路。

4. 发明申请

US20110284818A1 Graphene Channel-Based Devices and Methods for Fabrication Thereof 有权
标题翻译：石墨烯基通道设备及其制造方法
公开(公告)号：US20110284818A1
公开(公告)日：2011-11-24
申请号：US12783676
申请日：2010-05-20
申请人： Phaedon Avouris , Kuan-Neng Chen , Damon Farmer , Yu-Ming Lin
发明人： Phaedon Avouris , Kuan-Neng Chen , Damon Farmer , Yu-Ming Lin
IPC分类号： H01L29/16 , H01L21/04 , H01L21/98
CPC分类号： H01L21/50 , B82Y10/00 , B82Y40/00 , H01L21/8221 , H01L27/0688 , H01L27/092 , H01L27/1207 , H01L29/1606 , H01L29/66742 , H01L29/775 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
摘要翻译：提供了基于石墨烯基通道的器件及其制造技术。在一个方面，半导体器件包括：第一晶片，其具有形成在第一衬底上的至少一个石墨烯通道;围绕石墨烯通道的第一氧化物层;延伸穿过第一氧化物层的石墨烯通道的源极和漏极接触; 以及第二晶片，其具有形成在第二基板中的CMOS器件层，围绕所述CMOS器件层的第二氧化物层和延伸穿过所述第二氧化物层的所述CMOS器件层的多个触点，所述晶片通过氧化物层之间的氧化物 - 氧化物键。与CMOS器件层的一个或多个触点与源极和漏极触点接触。 CMOS器件层的一个或多个其它触点是用于石墨烯通道的栅极触点。

5. 发明授权

US08053782B2 Single and few-layer graphene based photodetecting devices 有权
标题翻译：基于单层和几层石墨烯的光电检测器件
公开(公告)号：US08053782B2
公开(公告)日：2011-11-08
申请号：US12546097
申请日：2009-08-24
申请人： Phaedon Avouris , Yu-Ming Lin , Thomas Mueller , Fengnian Xia
发明人： Phaedon Avouris , Yu-Ming Lin , Thomas Mueller , Fengnian Xia
IPC分类号： H01L29/15
CPC分类号： H01L51/428 , H01L29/1606 , H01L31/02327 , H01L31/035209 , H01L31/101 , Y02E10/549
摘要： A photodetector which uses single or multi-layer graphene as the photon detecting layer is disclosed. Multiple embodiments are disclosed with different configurations of electrodes. In addition, a photodetector array comprising multiple photodetecting elements is disclosed for applications such as imaging and monitoring.
摘要翻译：公开了使用单层或多层石墨烯作为光子检测层的光电探测器。公开了具有不同配置的电极的多个实施例。此外，公开了包括多个光电检测元件的光电探测器阵列，用于诸如成像和监视的应用。

6. 发明授权

US08629010B2 Carbon nanotube transistor employing embedded electrodes 有权
标题翻译：采用嵌入式电极的碳纳米管晶体管
公开(公告)号：US08629010B2
公开(公告)日：2014-01-14
申请号：US13278552
申请日：2011-10-21
申请人： Phaedon Avouris , Yu-Ming Lin , Mathias B. Steiner , Michael W. Engel , Ralph Krupke
发明人： Phaedon Avouris , Yu-Ming Lin , Mathias B. Steiner , Michael W. Engel , Ralph Krupke
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L51/0003 , H01L51/0048 , H01L51/0545
摘要： Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.
摘要翻译：碳纳米管可以与半导体制造工艺的兼容性相一致，具有用于形成较小器件的可扩展性，并且与结构损坏相关的性能下降不受影响。形成包括掩埋栅电极和两个嵌入电极的平面结构。在形成栅极电介质之后，沿着通过在两个嵌入电极之间施加电压而产生的交流（AC）电场的方向将碳纳米管组装在栅极电介质的表面上的溶液中。源极接触电极和漏极接触电极通过在碳纳米管的两端上沉积导电材料而形成。源极和漏极接触电极中的每一个可以与下面的嵌入式电极电短路以减小寄生电容。

7. 发明申请

US20130099204A1 CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES 有权
标题翻译：碳纳米管晶体管采用嵌入式电极
公开(公告)号：US20130099204A1
公开(公告)日：2013-04-25
申请号：US13278552
申请日：2011-10-21
申请人： Phaedon Avouris , Yu-Ming Lin , Mathias B. Steiner , Michael Engel , Ralph Krupke
发明人： Phaedon Avouris , Yu-Ming Lin , Mathias B. Steiner , Michael Engel , Ralph Krupke
IPC分类号： H01L29/775 , H01L21/336 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L51/0003 , H01L51/0048 , H01L51/0545
摘要： Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.
摘要翻译：碳纳米管可以与半导体制造工艺的兼容性相一致，具有用于形成较小器件的可扩展性，并且与结构损坏相关的性能下降不受影响。形成包括掩埋栅电极和两个嵌入电极的平面结构。在形成栅极电介质之后，沿着通过在两个嵌入电极之间施加电压而产生的交流（AC）电场的方向将碳纳米管组装在栅电介质的表面上的溶液中。源极接触电极和漏极接触电极通过在碳纳米管的两端上沉积导电材料而形成。源极和漏极接触电极中的每一个可以与下面的嵌入式电极电短路以减小寄生电容。

8. 发明申请

US20120056161A1 GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE 有权
标题翻译：具有自对准门的石墨晶体管
公开(公告)号：US20120056161A1
公开(公告)日：2012-03-08
申请号：US12876454
申请日：2010-09-07
申请人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
发明人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
IPC分类号： H01L29/76 , H01L21/335
CPC分类号： H01L29/1606 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/778 , H01L29/78684
摘要： A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.
摘要翻译：基于石墨烯的场效应晶体管包括与栅电极自对准的源极和漏极。在图案化的石墨烯层上沉积种子层和电介质金属氧化物层的堆叠。第一金属部分和第二金属部分的导电材料堆叠形成在电介质金属氧化物层的上方。使用第二金属部分横向蚀刻第一金属部分，去除电介质金属氧化物层的暴露部分以形成其中第二金属部分悬垂在第一金属部分上的栅极结构。移除晶种层并且在定向沉积工艺期间使用突出部来遮蔽栅极结构周围的近端区域，以形成与栅电极的边缘自对准且最小程度地横向间隔的源电极和漏电极。

9. 发明申请

US20090032803A1 METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR 有权
标题翻译：制备碳纳米管晶体的方法和装置
公开(公告)号：US20090032803A1
公开(公告)日：2009-02-05
申请号：US12164690
申请日：2008-06-30
申请人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
发明人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/721
摘要： A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method.
摘要翻译：一种制造具有单极特性和小的反向亚阈值斜率的纳米管场效应晶体管的方法包括在晶体管的漏极和源极之间的纳米管下面形成局部栅电极，并掺杂纳米管的部分。在另一实施例中，该方法包括在栅极电介质（例如，背栅极电介质）中形成至少一个沟槽和邻近局部栅电极的后栅极。本发明的另一方面是使用这种方法制造的纳米管场效应晶体管。

10. 发明申请

US20060255414A1 METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR HAVING UNIPOLAR CHARACTERISTICS 失效
标题翻译：制备具有单核特性的碳纳米管晶体管的方法和装置
公开(公告)号：US20060255414A1
公开(公告)日：2006-11-16
申请号：US11130313
申请日：2005-05-16
申请人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
发明人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/721
摘要： A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method.
摘要翻译：一种制造具有单极特性和小的反向亚阈值斜率的纳米管场效应晶体管的方法包括在晶体管的漏极和源极之间的纳米管下面形成局部栅电极，并掺杂纳米管的部分。在另一实施例中，该方法包括在栅极电介质（例如，背栅极电介质）中形成至少一个沟槽和邻近局部栅电极的后栅极。本发明的另一方面是使用这种方法制造的纳米管场效应晶体管。

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