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1. 发明授权

US4447873A Input-output buffers for a digital signal processing system 失效
标题翻译：用于数字信号处理系统的输入输出缓冲器
公开(公告)号：US4447873A
公开(公告)日：1984-05-08
申请号：US146934
申请日：1980-05-05
申请人： William L. Price , John C. Murtha , James A. Ross, Jr. , Clyde E. Adam , Kenneth R. Lucas
发明人： William L. Price , John C. Murtha , James A. Ross, Jr. , Clyde E. Adam , Kenneth R. Lucas
IPC分类号： G06F9/345 , G06F13/12 , G06F3/04 , G06F13/00
CPC分类号： G06F13/122 , G06F9/345
摘要： Input-output buffers interface a data terminal, such as a digital signal processor adapted to perform complex arithmetic functions on vectors of data words, with a storage controller. The input buffer interfaces the storage controller with the data terminal and generates control signals indicating when it is in condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer; and, further, generates signals indicating when it contains a complete vector of data at which time the input buffer will transfer the vector of data contained therein to the data terminal. Each output buffer interfaces the data terminal with the storage controller and generates control signals indicating when it is in condition to receive a vector of data whereon a vector of data will be transferred from the data terminal to the output buffer; and, further, generates signals indicating when it contains a complete vector of data at which time the output buffer will transfer the vector contained therein to the storage controller.
摘要翻译：输入输出缓冲器将数据终端（诸如适于对数据字的向量执行复杂算术功能的数字信号处理器）与存储控制器进行接口。所述输入缓冲器将所述存储控制器与所述数据终端接口，并产生指示何时从存储控制器接收数据字的向量的控制信号，所述存储控制器将所述数据向量传送到所述输入缓冲器; 并且还产生指示何时它包含完整的数据向量的信号，此时输入缓冲器将其中包含的数据的向量传送到数据终端。每个输出缓冲器将数据终端与存储控制器接口，并产生指示何时接收数据向量的条件的控制信号，其中数据向量将从数据终端传送到输出缓冲器; 并且还产生指示何时它包含完整的数据向量的信号，此时输出缓冲器将其中所包含的向量传送到存储控制器。

2. 发明授权

US4166289A Storage controller for a digital signal processing system 失效
标题翻译：数字信号处理系统的存储控制器
公开(公告)号：US4166289A
公开(公告)日：1979-08-28
申请号：US832775
申请日：1977-09-13
申请人： John C. Murtha , James A. Ross, Jr. , William G. Shipley , Martin W. Czekalski
发明人： John C. Murtha , James A. Ross, Jr. , William G. Shipley , Martin W. Czekalski
IPC分类号： G06F9/345 , G06F13/12 , G06F3/04 , G06F13/00
CPC分类号： G06F9/345 , G06F13/122
摘要： A storage controller for independently controlling the transfer of vectors of data into and out of a memory from a plurality of input devices and a digital signal processor capable of performing complex arithmetic functions. Program instructions, stored in the memory of the storage controller, specify the sequence of vector transfer between each device and the memory. The storage controller recognizes a request for a transfer of a vector of data from each device and selects one for a vector transfer according to predetermined priorities. The storage controller, under program control, repeats the execution of each program instruction word a predetermined number of times, generating upon each repeated execution a new address in the memory, whereby a vector of data is transferred between the memory and the selected device or vice versa. Each address generated by the storage controller during a vector transfer may be a certain increment from the preceding address generated whereby vectors of data may be stored in predetermined address locations in the memory and transferred out of the memory from different address locations.

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