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1. 发明授权

US06826670B2 Accessing memory units in a data processing apparatus 有权
标题翻译：访问数据处理设备中的存储器单元
公开(公告)号：US06826670B2
公开(公告)日：2004-11-30
申请号：US10158105
申请日：2002-05-31
申请人： Peter Guy Middleton , David Michael Bull , Gary Campbell
发明人： Peter Guy Middleton , David Michael Bull , Gary Campbell
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0215 , Y02D10/13
摘要： The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access. Instead, prediction logic is arranged to predict the one or more predetermined attributes, and clock generation logic is responsive to the predictive predetermined attributes from the prediction logic to select which one of the memory units is to be clocked during performance of the access, and to issue a clock signal to that memory unit. Checking logic is then provided to determine whether the predetermined attributes generated by the attribute generation logic agree with the predicted predetermined attributes, and if not, to reinitiate the access, in which event the clock generation logic is arranged to reselect one of the memory units using the predetermined attributes as determined by the attribute generation logic. This approach enables high speed processing of access requests, whilst achieving significant power savings over prior art systems where multiple memory units are clocked speculatively in parallel.
摘要翻译：本发明涉及用于访问数据处理装置中的存储单元的技术。数据处理装置包括用于存储数据值的多个存储器单元，用于发出指定对数据值对存储器单元进行访问的访问请求的处理器核心，以及用于执行由数据值指定的访问的存储器控制器访问请求。提供属性生成逻辑用于从访问请求确定一个或多个预定属性，以便在执行访问时验证哪个存储单元应被使用。然而，存储器控制器不等待直到在开始访问之前由属性生成逻辑执行这样的确定。相反，预测逻辑被布置为预测一个或多个预定属性，并且时钟生成逻辑响应来自预测逻辑的预测预定属性，以选择在执行访问期间要计时的哪个存储器单元，以及向该存储单元发出时钟信号。然后提供检查逻辑以确定由属性生成逻辑生成的预定属性是否与预测的预定属性一致，如果不是，则重新启动访问，在哪种情况下，时钟生成逻辑被设置为使用由属性生成逻辑确定的预定属性。这种方法可以实现对访问请求的高速处理，同时相对于其中多个存储器单元并行地推测地计时的现有技术系统实现显着的功率节省。

2. 发明授权

US06721861B2 Indicator of validity status information for data storage within a data processing system 有权
标题翻译：数据处理系统内数据存储的有效状态信息指示符
公开(公告)号：US06721861B2
公开(公告)日：2004-04-13
申请号：US10330478
申请日：2002-12-30
申请人： Peter Guy Middleton , David Michael Bull
发明人： Peter Guy Middleton , David Michael Bull
IPC分类号： G06F1200
CPC分类号： G06F12/0891 , G06F12/00
摘要： A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.
摘要翻译：提供有效存储器2，存储有效字8，其中位位置指示高速缓冲存储器7内相应的高速缓存线是否存储有效数据。提供触发器电路4以指示有效存储器2内的有效字8本身是否有效。对应于单个触发器电路4的有效字8的数量根据有效存储器2的大小而变化。因此，例如，单个触发器电路4可以指示是否有一个，两个，四个或八个有效来自有效存储器2的字8根据所采用的有效存储器2的特定尺寸来存储有效数据。

3. 发明授权

US06353879B1 Memory address translation in a data processing system 有权
标题翻译：数据处理系统中的内存地址转换
公开(公告)号：US06353879B1
公开(公告)日：2002-03-05
申请号：US09252927
申请日：1999-02-19
申请人： Peter Guy Middleton , David Michael Bull
发明人： Peter Guy Middleton , David Michael Bull
IPC分类号： G06F1200
CPC分类号： G06F12/10 , G06F12/1054 , G06F2212/654
摘要： A data processing system 2 is provided with a processor core 4 that issues virtual addresses VA that are translated to mapped addresses MA by an address translation circuit 6 based upon a predicted address mapping. The mapped address MA is used for a memory access within a memory system 8. The mapped address MA starts to be used before a mapping validity circuit 6 has determined whether or not the predicted translation was valid. Accordingly, if the predicted address translation turns out to be invalid, then the memory access is aborted. The state of the processor core is preserved either by stretching the processor clock signal or by continuing the processor clock signal and waiting the processor 4. The memory system 8 then restarts the memory access with the correct translated address.
摘要翻译：数据处理系统2具有处理器核心4，处理器核心4基于预测的地址映射，通过地址转换电路6发布被映射到映射地址MA的虚拟地址VA。映射地址MA用于存储器系统8内的存储器访问。映射地址MA开始在映射有效性电路6确定预测翻译是否有效之前被使用。因此，如果预测的地址转换是无效的，则存储器访问被中止。通过拉伸处理器时钟信号或继续处理器时钟信号并等待处理器4来保留处理器核心的状态。然后，存储器系统8以正确翻译的地址重新启动存储器访问。

4. 发明授权

US06532553B1 Debugging data processing systems 有权
标题翻译：调试数据处理系统
公开(公告)号：US06532553B1
公开(公告)日：2003-03-11
申请号：US09407846
申请日：1999-09-29
申请人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
发明人： David John Gwilt , Andrew Christopher Rose , Peter Guy Middleton , David Michael Bull
IPC分类号： H02H305
CPC分类号： G06F11/3636 , G06F9/30003 , G06F9/3005
摘要： A data processing system is provided having a main processor 4 and a coprocessor 26. When in a debug mode, the main processor 4 and the coprocessor 26 are supplied with different instructions. The coprocessor 26 is supplied with a coprocessor debug data generation instruction (MCR) whilst the main processor 4 is supplied with a main processor data capture instruction (LDR). The coprocessor 26 responds to the MCR instruction by controlling debug data representing state of the data processing apparatus 2 to be placed upon a data bus 24 from where it is read by the main processor 4 under control of the LDR instruction.
摘要翻译：提供了具有主处理器4和协处理器26的数据处理系统。当处于调试模式时，向主处理器4和协处理器26提供不同的指令。协处理器26被提供有协处理器调试数据生成指令（MCR），而主处理器4被提供有主处理器数据捕获指令（LDR）。协处理器26通过控制表示数据处理装置2的状态的调试数据来响应MCR指令，数据处理装置2将被放置在数据总线24上，从LDR指令的控制下由主处理器4读取数据总线24。

5. 发明授权

US09519538B2 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US09519538B2
公开(公告)日：2016-12-13
申请号：US13067510
申请日：2011-06-06
申请人： Emre Özer , Shidhartha Das , David Michael Bull
发明人： Emre Özer , Shidhartha Das , David Michael Bull
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F11/07 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.
摘要翻译：具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。部分错误恢复可能是从指令流水线中刷新上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在可用主存储元件来适当地捕获与以下程序指令对应的信号值。

6. 发明授权

US08640008B2 Error recovery in a data processing apparatus 有权
标题翻译：数据处理设备中的错误恢复
公开(公告)号：US08640008B2
公开(公告)日：2014-01-28
申请号：US13336428
申请日：2011-12-23
申请人： Guillaume Schon , Luca Scalabrino , Frederic Claude Marie Piry , David Michael Bull
发明人： Guillaume Schon , Luca Scalabrino , Frederic Claude Marie Piry , David Michael Bull
IPC分类号： H03M13/00
CPC分类号： G06F11/1407 , G06F11/1497
摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
摘要翻译：数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。错误恢复电路如果错误值被确认则启动指令的重新执行。计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。

7. 发明授权

US08621272B2 Integrated circuit with error repair and fault tolerance 有权
公开(公告)号：US08621272B2
公开(公告)日：2013-12-31
申请号：US12735339
申请日：2008-12-29
申请人： Shidhartha Das , David Michael Bull , Emre Ozer
发明人： Shidhartha Das , David Michael Bull , Emre Ozer
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

8. 发明申请

US20120131313A1 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US20120131313A1
公开(公告)日：2012-05-24
申请号：US13067510
申请日：2011-06-06
申请人： Emre Ozer , Shidhartha Das , David Michael Bull
发明人： Emre Ozer , Shidhartha Das , David Michael Bull
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译：提供了指令处理流水线6。这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联，这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值程序指令。这样可以避免冲洗。

9. 发明授权

US08185812B2 Single event upset error detection within an integrated circuit 有权
标题翻译：集成电路内的单事件镦粗错误检测
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
申请人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
发明人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译：集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

10. 发明授权

US07895469B2 Integrated circuit using speculative execution 有权
标题翻译：集成电路采用推测执行
公开(公告)号：US07895469B2
公开(公告)日：2011-02-22
申请号：US12285796
申请日：2008-10-14
申请人： Emre Özer , David Michael Bull , Shidhartha Das
发明人： Emre Özer , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F9/3842 , G06F9/3861 , G06F9/3869
摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.
摘要翻译：集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗）基于错误。流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。该预测用于触发第二次错误恢复操作（部分流水线停止）。该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

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