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    • 4. 发明授权
    • Semiconductor power component and a method of producing same
    • 半导体功率元件及其制造方法
    • US06949439B2
    • 2005-09-27
    • US10450222
    • 2002-03-26
    • Peter FlohrsRobert PlikatWolfgang Feiler
    • Peter FlohrsRobert PlikatWolfgang Feiler
    • H01L21/331H01L29/739H01L21/8224
    • H01L29/66333H01L29/7395
    • A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 μm.
    • 半导体功率部件和半导体功率部件的制造方法,特别是用于点火应用的垂直NPT-IGBT,击穿电压小于约。 半导体功率部件包括第一导电类型的晶片衬底,其包括第二导电类型的后侧发射极区域和第一导电类型的前侧漂移区域; 背面阳极接触件,其连接到发射极区域并部分地延伸到前侧表面; 前端MOS控制结构; 以及连接到前侧MOS控制结构的前侧源极区域和主体区域的前侧阴极接触件。 在限定的击穿电压下,漂移区的厚度远大于空间电荷区的宽度; 后侧发射极区域的厚度大于5μm。
    • 6. 发明授权
    • Monolithically integrated semiconductor arrangement with a cover
electrode
    • 具有覆盖电极的单片集成半导体布置
    • US5479046A
    • 1995-12-26
    • US263951
    • 1994-06-22
    • Peter FlohrsChristian Pluntke
    • Peter FlohrsChristian Pluntke
    • H01L29/06H01L29/40H01L29/78H01L29/772
    • H01L29/402H01L29/0615H01L29/7813
    • The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.-) underneath the cover electrode (D).
    • 本发明涉及一种单片集成半导体装置,其中从第一主表面将第一区(p)和第二区(n +)扩散到基底(2)内,该衬底(2)是弱掺杂(衬底区n- 第一主表面(3)并且在第二主表面(4)下更强掺杂(衬底区域n +)。 绝缘钝化层附着到第一主表面(3)上,其上面设有覆盖相邻衬底区域(n-)和第一区域(p)的边缘区域的金属覆盖电极(D)和 第二区(n +)。 根据本发明,与相关区(n +)具有相同类型导电性但具有较弱掺杂的至少一个附加区(nu)被扩散用于增加突破电压,并连接到区 (n +)不接触另一区域(p),并且防止区域(n +)直接与覆盖电极(D)下方的衬底(n-)接壤。
    • 10. 发明授权
    • Integrated Darlington transistor combination including auxiliary
transistor and Zener diode
    • 集成达林顿晶体管组合,包括辅助晶体管和齐纳二极管
    • US4564771A
    • 1986-01-14
    • US511154
    • 1983-07-06
    • Peter Flohrs
    • Peter Flohrs
    • H03F3/347H01L27/082H03F3/34H03F3/60H03K17/082H03K17/14H03K17/60
    • H01L27/0825H03K17/0826H03K17/14
    • In a three-stage Darlington transistor circuit, the base of the middle transistor is connected to the series combination of a resistance and a Zener diode, with the Zener diode anode being connected to the resistance. A voltage divider is provided between the collector and emitter of the power transistor. For reducing the loading and deviation from nominal value of the voltage divider with change of temperature, an auxiliary transistor (T.sub.4) is provided having its base connected to one tap of the voltage divider and its emitter to the cathode of the Zener diode. The collector of the auxiliary transistor is provided in the integrated circuit substrate in common with the collectors of the transistors of the Darlington circuit. The other tap of the voltage divider is provided for emitter-collector clamping voltage purposes.
    • 在三阶段达林顿晶体管电路中,中间晶体管的基极连接到电阻和齐纳二极管的串联组合,齐纳二极管阳极连接到电阻。 在功率晶体管的集电极和发射极之间提供一个分压器。 为了减小负载和偏离温度变化的分压器额定值,提供辅助晶体管(T4),其基极连接到分压器的一个抽头,其发射极连接到齐纳二极管的阴极。 辅助晶体管的集电极与达林顿电路的晶体管的集电极共同设置在集成电路基板中。 分压器的另一个分接头用于发射极 - 集电极钳位电压目的。