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1. 发明授权

US6137124A Integrated vertical semiconductor component 失效
标题翻译：集成垂直半导体元件
公开(公告)号：US6137124A
公开(公告)日：2000-10-24
申请号：US963447
申请日：1997-11-03
申请人： Hartmut Michel , Peter Flohrs , Christian Pluntke , Alfred Goerlach , Anton Mindl , Ning Qu
发明人： Hartmut Michel , Peter Flohrs , Christian Pluntke , Alfred Goerlach , Anton Mindl , Ning Qu
IPC分类号： H01L23/58 , H01L29/80 , H01L29/8605 , H01L29/772 , H01L29/745 , H01L29/808
CPC分类号： H01L29/8605
摘要： A vertical semiconductor component has an integrated switching device, which delivers an electric value correlating with the rear potential. The semiconductor component includes a doping region with a hole, which is free of the doping atoms of the doping region. The hole, when properly sized and contacted, can supply an electric current correlating with the rear potential.
摘要翻译：垂直半导体部件具有集成开关器件，其提供与后部电势相关的电气值。半导体元件包括具有空穴的掺杂区，其没有掺杂区的掺杂原子。该孔在适当的尺寸和接触时可以提供与后方电位相关的电流。

2. 发明授权

US5449949A Monolithic integrated semiconductor device 失效
标题翻译：单片集成半导体器件
公开(公告)号：US5449949A
公开(公告)日：1995-09-12
申请号：US74874
申请日：1993-06-11
申请人： Hartmut Michel , Peter Flohrs , Alfred Goerlach
发明人： Hartmut Michel , Peter Flohrs , Alfred Goerlach
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/40 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/861
CPC分类号： H01L27/0825 , H01L29/402 , H01L29/7813
摘要： A monolithic integrated semiconductor is proposed, in which on the main surface of a monolithically integrated n-p-n transistor or p-n-p transistor, a cover electrode (D1) is mounted for internal voltage limitation, covering only a single junction region between a highly doped zone (5) and the weakly doped substrate (1). An adjacent highly doped zone (4) is not covered by the cover electrode (D1). By connecting the metal cover electrode (D1) to the pickup (12) for a voltage divider (R1, R2), a breakdown voltage can be adjusted that is higher than the sum of the depletion breakdown voltage and the enhancement breakdown voltage.
摘要翻译： PCT No.PCT / DE91 / 00909 Sec。 371日期：1993年6月11日 102（e）日期1993年6月11日PCT 1991年11月19日PCT公布。公开号WO92 / 10855 日期：1992年6月25日。提出了一种单片集成半导体，其中在单片集成的npn晶体管或pnp晶体管的主表面上安装用于内部电压限制的覆盖电极（D1），仅覆盖高掺杂区（5）和弱掺杂衬底（1）。相邻的高掺杂区（4）不被覆盖电极（D1）覆盖。通过将金属盖电极（D1）连接到用于分压器（R1，R2）的拾取器（12），可以调节高于耗尽击穿电压和增强击穿电压之和的击穿电压。

3. 发明申请

US20090206438A1 Semiconductor component 有权
标题翻译：半导体元件
公开(公告)号：US20090206438A1
公开(公告)日：2009-08-20
申请号：US11664857
申请日：2005-09-12
申请人： Peter Flohrs , Alfred Goerlach , Peter Urbach , Wolfgang Feiler , Ning Qu , Klaus Heyers
发明人： Peter Flohrs , Alfred Goerlach , Peter Urbach , Wolfgang Feiler , Ning Qu , Klaus Heyers
IPC分类号： H01L29/66 , H01L21/24 , H01L21/50
CPC分类号： H01L28/20 , G01K7/22 , H01L27/0802 , H01L29/8605 , H01L29/8611
摘要： A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
摘要翻译：一种半导体元件及其制造方法，该半导体元件具有很大程度上取决于温度的电阻特性。该电阻特性通过半导体元件的特殊的多层结构获得，一层被设计成例如在n掺杂区域中存在多个p掺杂区域，所述区域被短路在一侧通过金属镀层。例如，半导体组件可以用于通过集成到导体中来减小电流峰值。在冷态中，当由于流动电流而加热半导体元件时，半导体元件具有高电阻，其变得明显较低。

4. 发明授权

US08072043B2 Semiconductor component 有权
标题翻译：半导体元件
公开(公告)号：US08072043B2
公开(公告)日：2011-12-06
申请号：US11664857
申请日：2005-09-12
申请人： Peter Flohrs , Alfred Goerlach , Peter Urbach , Wolfgang Feiler , Ning Qu , Klaus Heyers
发明人： Peter Flohrs , Alfred Goerlach , Peter Urbach , Wolfgang Feiler , Ning Qu , Klaus Heyers
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , G01K7/22 , H01L27/0802 , H01L29/8605 , H01L29/8611
摘要： A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, one layer being designed in such a way that, for example, multiple p-doped regions are present in an n-doped region, said regions being short-circuited on one side via a metal-plated layer. For example, the semiconductor component may be used for reducing current peaks, by being integrated into a conductor. In the cold state, the semiconductor component has a high resistance which becomes significantly lower when the semiconductor component is heated as a result of the flowing current.
摘要翻译：一种半导体元件及其制造方法，该半导体元件具有很大程度上取决于温度的电阻特性。该电阻特性通过半导体元件的特殊的多层结构获得，一层被设计成例如在n掺杂区域中存在多个p掺杂区域，所述区域被短路在一侧通过金属镀层。例如，半导体组件可以用于通过集成到导体中来减小电流峰值。在冷态中，当由于流动电流而加热半导体元件时，半导体元件具有高电阻，其变得明显较低。

5. 发明授权

US4916494A Monolithic integrated planar semiconductor system and process for making the same 失效
标题翻译：单片集成平面半导体系统及其制造方法
公开(公告)号：US4916494A
公开(公告)日：1990-04-10
申请号：US107855
申请日：1987-10-06
申请人： Peter Flohrs , Hartmut Michel
发明人： Peter Flohrs , Hartmut Michel
IPC分类号： H01L21/02 , H01L27/082 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/8605
CPC分类号： H01L29/402 , H01L27/0825 , H01L28/20 , H01L29/7813 , H01L29/8605
摘要： A monolithic integrated semiconductor device is described, wherein for the adjustment of the breakdown voltage a cover electrode (7) is disposed in the area of the pn-junctions and a corresponding potential is applied through a voltage divider (1) for adjusting the breakdown voltage. For maintaining a temperature independent breakdown voltage it is provided that the voltage divider (1) consists of resistors (R1, R2) in the form of diffused zones which have different doping levels. The resulting different temperature coefficients of the resistors (R1,R2) of the voltage divider cause a temperature dependent potential change of the cover electrode potential, whereby a temperature stabilization of the breakdown voltage is obtained.
摘要翻译：描述了一种单片集成半导体器件，其中为了调节击穿电压，覆盖电极（7）设置在pn结的区域中，并且相应的电位通过分压器（1）施加以调节击穿电压。为了保持独立于温度的击穿电压，分压器（1）由具有不同掺杂水平的扩散区形式的电阻（R1，R2）组成。所得到的分压器的电阻器（R1，R2）的不同温度系数导致覆盖电极电位的温度依赖性电位变化，从而获得击穿电压的温度稳定。

6. 发明授权

US4886985A Transistor arrangement with an output transistor 失效
标题翻译：具有输出晶体管的晶体管布置
公开(公告)号：US4886985A
公开(公告)日：1989-12-12
申请号：US307089
申请日：1988-12-23
申请人： Peter Flohrs , Klaus Heyke , Hartmut Michel , Ulrich Nelle
发明人： Peter Flohrs , Klaus Heyke , Hartmut Michel , Ulrich Nelle
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L27/08 , H01L27/082 , H01L29/732 , H03K17/04 , H03K17/0422 , H03K17/64
CPC分类号： H03K17/0422 , H01L27/0821
摘要： A transistor arrangement, particularly for the fast switching of inductive loads, includes a driving first transistor and a power output second transistor (T1, T2) interconnected as a Darlington pair having a base terminal, an emitter terminal and a collector terminal. A third transistor (T3) has its collector connected to the base of the first transistor (T1) and its emitter connected to the emitter terminal (E). A fourth transistor (T4) of a conductivity type opposite to that of the first, second and third transistors has its base connected to the collector terminal, its emitter connected to the base terminal, and its collector connected to the base of the third transistor (T3). This structure is particularly suited for a monolithic integration.
摘要翻译： PCT No.PCT / DE87 / 00217 Sec。 371日期：1988年12月23日第 102（e）日期1988年12月23日PCT提交1987年5月9日PCT公布。第WO88 / 00413号公报特别是用于感性负载的快速切换的晶体管布置包括驱动第一晶体管和作为达林顿对互连的功率输出第二晶体管（T1，T2），其具有基极端子，发射极端子和集电极端子。第三晶体管（T3）的集电极连接到第一晶体管（T1）的基极，其发射极连接到发射极端子（E）。与第一，第二和第三晶体管相反的导电类型的第四晶体管（T4）的基极连接到集电极端子，其发射极连接到基极端子，其集电极连接到第三晶体管的基极（ T3）。该结构特别适用于单片集成。

7. 发明授权

US4695867A Monolithically integrated planar semiconductor arrangement 失效
标题翻译：单片集成平面半导体布置
公开(公告)号：US4695867A
公开(公告)日：1987-09-22
申请号：US775044
申请日：1985-08-21
申请人： Peter Flohrs , Hartmut Michel
发明人： Peter Flohrs , Hartmut Michel
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L23/528 , H01L27/082 , H01L29/06 , H01L29/40 , H01L27/02
CPC分类号： H01L29/402 , H01L23/528 , H01L27/0825 , H01L2924/0002
摘要： A semiconductor arrangement is suggested which is provided with a capacity transistor and a drive transistor in form of a Dralington-circuit. Thereby, the two transistors are monolithically integrated with a planar technique in a common substrate (8), which forms the two collector zones of the two transistors (T1,T2). A passivation layer (14) covers the main face of substrate (8) covering this main surface with the exception of contact windows. A cover electrode (13) is disposed above the passivation layer in the area between the collector zone and the base zone (4) of the capacity transistor (T2), whereby this passivation layer is connected with a resistor strip (2) at a distance from the base zone (4) for adjusting its potential. An additional guard strip (3) is diffused into the main surface between the resistor strip (2) and the base zone (4). In order to prevent a voltage rupture in the area of the resistor strip (2), the passivation layer is designed thinner at the area adjacent the base zone (4) than in the remaining area beneath the cover electrode (13).
摘要翻译： PCT No.PCT / DE85 / 00118 Sec。 371日期1985年8月21日 102（e）1985年8月21日PCT PCT公布1985年4月16日PCT公布。出版物WO85 / 05497 日期为1985年12月5日。提出了一种半导体装置，其具有容量晶体管和Dralington电路形式的驱动晶体管。由此，两个晶体管在共同的衬底（8）中与平面技术单片集成，形成两个晶体管（T1，T2）的两个集电极区。除了接触窗外，钝化层（14）覆盖覆盖该主表面的基板（8）的主面。覆盖电极（13）设置在容纳晶体管（T2）的集电区域和基极区域（4）之间的区域中的钝化层上方，由此该钝化层与电阻条（2）在一定距离处连接从基区（4）调整其电位。附加的保护条（3）扩散到电阻条（2）和基区（4）之间的主表面。为了防止电阻条（2）的区域中的电压破裂，钝化层在与基极区（4）相邻的区域比在覆盖电极（13）下方的剩余区域更薄。

8. 发明授权

US5479046A Monolithically integrated semiconductor arrangement with a cover electrode 失效
标题翻译：具有覆盖电极的单片集成半导体布置
公开(公告)号：US5479046A
公开(公告)日：1995-12-26
申请号：US263951
申请日：1994-06-22
申请人： Peter Flohrs , Christian Pluntke
发明人： Peter Flohrs , Christian Pluntke
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L29/772
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/7813
摘要： The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.-) underneath the cover electrode (D).
摘要翻译：本发明涉及一种单片集成半导体装置，其中从第一主表面将第一区（p）和第二区（n +）扩散到基底（2）内，该衬底（2）是弱掺杂（衬底区n- 第一主表面（3）并且在第二主表面（4）下更强掺杂（衬底区域n +）。绝缘钝化层附着到第一主表面（3）上，其上面设有覆盖相邻衬底区域（n-）和第一区域（p）的边缘区域的金属覆盖电极（D）和第二区（n +）。根据本发明，与相关区（n +）具有相同类型导电性但具有较弱掺杂的至少一个附加区（nu）被扩散用于增加突破电压，并连接到区（n +）不接触另一区域（p），并且防止区域（n +）直接与覆盖电极（D）下方的衬底（n-）接壤。

9. 发明授权

US06949439B2 Semiconductor power component and a method of producing same 失效
标题翻译：半导体功率元件及其制造方法
公开(公告)号：US06949439B2
公开(公告)日：2005-09-27
申请号：US10450222
申请日：2002-03-26
申请人： Peter Flohrs , Robert Plikat , Wolfgang Feiler
发明人： Peter Flohrs , Robert Plikat , Wolfgang Feiler
IPC分类号： H01L21/331 , H01L29/739 , H01L21/8224
CPC分类号： H01L29/66333 , H01L29/7395
摘要： A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 μm.
摘要翻译：半导体功率部件和半导体功率部件的制造方法，特别是用于点火应用的垂直NPT-IGBT，击穿电压小于约。半导体功率部件包括第一导电类型的晶片衬底，其包括第二导电类型的后侧发射极区域和第一导电类型的前侧漂移区域; 背面阳极接触件，其连接到发射极区域并部分地延伸到前侧表面; 前端MOS控制结构; 以及连接到前侧MOS控制结构的前侧源极区域和主体区域的前侧阴极接触件。在限定的击穿电压下，漂移区的厚度远大于空间电荷区的宽度; 后侧发射极区域的厚度大于5μm。

10. 发明授权

US5866951A Hybrid circuit with an electrically conductive adhesive 失效
标题翻译：具有导电粘合剂的混合电路
公开(公告)号：US5866951A
公开(公告)日：1999-02-02
申请号：US39120
申请日：1993-04-12
申请人： Lothar Gademann , Peter Flohrs , Juergen Hartmann
发明人： Lothar Gademann , Peter Flohrs , Juergen Hartmann
IPC分类号： H01L21/56 , H01L21/60 , H01L21/98 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/563 , H01L24/29 , H01L24/83 , H01L25/50 , H01L2224/16225 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/73203 , H01L2224/83192 , H01L2224/838 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/19043
摘要： The composite hybrid semiconductor structure contains a support plate substrate (11) with a number of at least two support connector spots (13) and a semiconductor chip or semiconductor wafer substrate (10) with a number of at least two chip connector spots (16). The structures is distinguished by a respectively thermally and electrically conducting adhesive layer (13') on the surface of the support plate substrate (11) within the areas of the support connector spots (13), where the said substrates (10, 11) with the said connector spots (13, 16) placed opposite each other and in electrically conducting and mechanically firm connection have been brought into connection with each other by the said electrically conductive adhesive layers (13').
摘要翻译：复合混合半导体结构包括具有多个至少两个支撑连接器点（13）的支撑板基板（11）和具有多个至少两个芯片连接器点（16）的半导体芯片或半导体晶片基板（10）。这些结构的特征在于在支撑连接器点（13）的区域内的支撑板基板（11）的表面上的分别导热和导电的粘合剂层（13'），其中所述基板（10,11）具有通过所述导电粘合剂层（13'）使彼此相对放置并且导电和机械牢固连接的所述连接器点（13,16）彼此连接。

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