专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

2. 发明授权

US5923857A Method and apparatus for ordering writeback data transfers on a bus 失效
标题翻译：在总线上订购回写数据传输的方法和装置
公开(公告)号：US5923857A
公开(公告)日：1999-07-13
申请号：US708922
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
IPC分类号： G06F12/08 , G06F13/14 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.
摘要翻译：用于排序数据传输的方法和装置包括从请求代理接收的数据的关键部分的标识符以及数据请求。然后将与所请求的数据相对应的回写数据作为多个部分传送到总线，并被排序以确保包括数据的关键部分的第一部分首先被传送到总线。

3. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

4. 发明授权

US5615343A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5615343A
公开(公告)日：1997-03-25
申请号：US302600
申请日：1994-09-08
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

5. 发明授权

US06405271B1 Data flow control mechanism for a bus supporting two-and three-agent transactions 失效
标题翻译：支持二代理和三代理交易的总线数据流控制机制
公开(公告)号：US06405271B1
公开(公告)日：2002-06-11
申请号：US08709215
申请日：1996-09-06
申请人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
发明人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
IPC分类号： G06F1300
CPC分类号： G06F13/368 , G06F13/36 , G06F13/37 , G06F13/4213
摘要： A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.
摘要翻译：支持二代理和三代理交易的总线的数据流控制机制包括一个将请求的指示置于计算机系统总线上的控制逻辑。在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自耦合到总线的另一代理程序的指示，即其他代理程序准备好接收数据。

6. 发明授权

US5784579A Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 失效
标题翻译：基于总线管线深度从总线代理动态控制总线访问的方法和装置
公开(公告)号：US5784579A
公开(公告)日：1998-07-21
申请号：US709214
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
IPC分类号： G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4027 , G06F13/4217
摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.
摘要翻译：动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。耦合到总线的代理包括发射机和接收机。发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

7. 发明授权

US5911053A Method and apparatus for changing data transfer widths in a computer system 失效
标题翻译：用于在计算机系统中改变数据传输宽度的方法和装置
公开(公告)号：US5911053A
公开(公告)日：1999-06-08
申请号：US723572
申请日：1996-09-30
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Gurbir Singh
IPC分类号： G06F13/40 , G06F3/00
CPC分类号： G06F13/4018
摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.
摘要翻译：在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。然后基于第一指示和第二指示确定数据传输宽度。根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。然后基于第一，第二和第三指示确定数据传送宽度。

8. 发明授权

US06253302B1 Method and apparatus for supporting multiple overlapping address spaces on a shared bus 失效
公开(公告)号：US06253302B1
公开(公告)日：2001-06-26
申请号：US08705684
申请日：1996-08-29
申请人： Peter D. MacWilliams , Stephen S. Pawlowski
发明人： Peter D. MacWilliams , Stephen S. Pawlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1016 , G06F12/0623
摘要： A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

9. 发明授权

US06807592B2 Quad pumped bus architecture and protocol 失效
标题翻译：四泵浦总线架构和协议
公开(公告)号：US06807592B2
公开(公告)日：2004-10-19
申请号：US09925691
申请日：2001-08-10
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
摘要翻译：双向多点处理器总线连接到多个总线代理。可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。驱动代理还激活选通以识别信息元素的采样点。可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

10. 发明授权

US06804735B2 Response and data phases in a highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构中的响应和数据阶段
公开(公告)号：US06804735B2
公开(公告)日：2004-10-12
申请号：US09784244
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据忙信号用于事务N-1，并取消对数据忙信号的否定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式