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1. 发明授权

US5796977A Highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构
公开(公告)号：US5796977A
公开(公告)日：1998-08-18
申请号：US688238
申请日：1996-07-29
申请人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/18 , G06F12/00 , G06F13/00
CPC分类号： G06F13/18 , G06F12/0831
摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
摘要翻译：描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

2. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

3. 发明授权

US5615343A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5615343A
公开(公告)日：1997-03-25
申请号：US302600
申请日：1994-09-08
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

4. 发明授权

US5784579A Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 失效
标题翻译：基于总线管线深度从总线代理动态控制总线访问的方法和装置
公开(公告)号：US5784579A
公开(公告)日：1998-07-21
申请号：US709214
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
IPC分类号： G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4027 , G06F13/4217
摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.
摘要翻译：动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。耦合到总线的代理包括发射机和接收机。发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

5. 发明授权

US5923857A Method and apparatus for ordering writeback data transfers on a bus 失效
标题翻译：在总线上订购回写数据传输的方法和装置
公开(公告)号：US5923857A
公开(公告)日：1999-07-13
申请号：US708922
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
发明人： Stephen S. Pawlowski , Peter D. MacWilliams , Nitin V. Sarangdhar , Gurbir Singh
IPC分类号： G06F12/08 , G06F13/14 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.
摘要翻译：用于排序数据传输的方法和装置包括从请求代理接收的数据的关键部分的标识符以及数据请求。然后将与所请求的数据相对应的回写数据作为多个部分传送到总线，并被排序以确保包括数据的关键部分的第一部分首先被传送到总线。

6. 发明授权

US06405271B1 Data flow control mechanism for a bus supporting two-and three-agent transactions 失效
标题翻译：支持二代理和三代理交易的总线数据流控制机制
公开(公告)号：US06405271B1
公开(公告)日：2002-06-11
申请号：US08709215
申请日：1996-09-06
申请人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
发明人： Peter D. MacWilliams , Nitin V. Sarangdhar , Stephen S. Pawlowski , Gurbir Singh
IPC分类号： G06F1300
CPC分类号： G06F13/368 , G06F13/36 , G06F13/37 , G06F13/4213
摘要： A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.
摘要翻译：支持二代理和三代理交易的总线的数据流控制机制包括一个将请求的指示置于计算机系统总线上的控制逻辑。在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自耦合到总线的另一代理程序的指示，即其他代理程序准备好接收数据。

7. 发明授权

US5809524A Method and apparatus for cache memory replacement line identification 失效
标题翻译：用于高速缓存存储器替换线路识别的方法和装置
公开(公告)号：US5809524A
公开(公告)日：1998-09-15
申请号：US822044
申请日：1997-03-24
申请人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
发明人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/123 , G06F12/0831
摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.
摘要翻译：一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。该接口包括地址总线，数据总线和状态总线。地址总线将请求的地址从控制器传送到高速缓冲存储器。数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。

8. 发明授权

US5701503A Method and apparatus for transferring information between a processor and a memory system 失效
标题翻译：用于在处理器和存储器系统之间传送信息的方法和装置
公开(公告)号：US5701503A
公开(公告)日：1997-12-23
申请号：US360331
申请日：1994-12-21
申请人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
发明人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , G06F12/0831
摘要： A method and apparatus for transferring information between a processor and a memory system utilizing a chunk write buffer, where read and write requests to the L2 cache memory are controlled by the processor. The cache line associated with each such request is larger than the interface coupling the L2 cache memory and the processor. Read requests are returned from the L2 cache memory to the processor in burst fashion. Write requests are transferred from the processor to the L2 cache memory during clock cycles in which the processor does not require the interface for a read request. Write requests need not be transferred in burst fashion; rather, a portion of the write request corresponding to the size of the interface, referred to as a chunk, is transferred from the processor to the L2 cache memory and stored temporarily in the chunk write buffer. When the processor has transferred the entire cache line to the L2 cache memory, the processor signals the L2 cache memory to transfer the contents of the chunk write buffer into the data array of the cache memory.
摘要翻译：一种利用块写入缓冲器在处理器和存储器系统之间传送信息的方法和装置，其中对L2高速缓冲存储器的读取和写入请求由处理器控制。与每个这样的请求相关联的高速缓存行大于耦合L2高速缓冲存储器和处理器的接口。读取请求以突发方式从L2高速缓冲存储器返回到处理器。在处理器不需要读取请求的接口的时钟周期期间，写入请求从处理器传送到L2高速缓冲存储器。写请求不需要以突发方式传输; 相反，与被称为块的接口的大小相对应的写入请求的一部分从处理器传送到L2高速缓冲存储器，并临时存储在块写入缓冲器中。当处理器将整个高速缓存行传输到L2高速缓冲存储器时，处理器发信号通知L2缓存存储器，以将块写入缓冲器的内容传送到高速缓冲存储器的数据阵列中。

9. 发明授权

US5937171A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5937171A
公开(公告)日：1999-08-10
申请号：US669101
申请日：1996-06-26
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42 , H04L12/417 , G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

10. 发明授权

US5715428A Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system 失效
标题翻译：用于在多处理器计算机系统中维持多级高速缓存层级一致性的装置
公开(公告)号：US5715428A
公开(公告)日：1998-02-03
申请号：US639719
申请日：1996-04-29
申请人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Nitin V. Sarangdhar , John M. Bauer , Mandar S. Joshi , Ashwani K. Gupta
发明人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Nitin V. Sarangdhar , John M. Bauer , Mandar S. Joshi , Ashwani K. Gupta
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions. State transitions depend on both processor generated activities and activities by other bus agents, including other processors. Data consistency is guaranteed in systems having multiple levels of cache and shared memory and/or multiple active agents, such that no agent ever reads stale data and actions are serialized as needed.
摘要翻译：一种计算机系统，包括具有高速缓存层级的多个高速缓存代理，所述高速缓存代理器通过系统总线共享存储器并根据协议发出存储器访问请求，其中高速缓存行具有包括多条线路之一的当前状态状态。多个行状态包括修改的（M）状态，其中M状态的第一高速缓存代理的行具有比系统中的任何其他副本更新的数据; 排除（E）状态，其中第一高速缓存代理中的E状态中的线是系统中唯一具有高速缓存行中的数据的副本的代理，第一高速缓存代理将数据修改为所述高速缓存行独立于耦合到所述系统总线的其它所述代理; 共享（S）状态，其中S状态的行指示多于一个代理具有该行中的数据的副本; 和指示该行不存在于缓存中的无效（I）状态。对I状态的行进行读取或写入会导致高速缓存未命中。本发明将状态与线相关联并且定义了管理状态转换的规则。状态转换取决于处理器生成的活动和其他总线代理（包括其他处理器）的活动。在具有多级缓存和共享内存和/或多个活动代理的系统中保证数据一致性，使得任何代理程序都不会读取过时的数据，并且操作根据需要进行序列化。

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