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1. 发明授权

US6055656A Control register bus access through a standardized test access port 失效
标题翻译：控制寄存器总线访问通过标准化测试访问端口
公开(公告)号：US6055656A
公开(公告)日：2000-04-25
申请号：US434163
申请日：1995-05-02
申请人： James A. Wilson, Jr. , Anthony C. Miller , Michael W. Rhodehamel , Adrian Carbine , Derek B. I. Feltham , Sumeet Agrawal
发明人： James A. Wilson, Jr. , Anthony C. Miller , Michael W. Rhodehamel , Adrian Carbine , Derek B. I. Feltham , Sumeet Agrawal
IPC分类号： G01R31/3185 , G06F11/267 , G01R31/28
CPC分类号： G06F11/2236 , G01R31/318572
摘要： A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.
摘要翻译：用于通过配置成建立的测试标准的测试访问端口访问控制寄存器总线和微处理器的控制寄存器的方案。微处理器的测试访问端口（TAP）被配置为基于IEEE 1149.1标准中规定的技术来串行地进行通信。外部串行指令被转换为并行传输，以提供用于访问内部结构的控制信号。串行地址和数据信号也被转换为并行传输以访问控制寄存器总线上的内部结构，并行输出转换为用于外部输出的串行格式。通过允许外部访问低级内部总线架构，可以通过利用外部编程来执行系统测试和调试。

2. 发明授权

US5832534A Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories 失效
公开(公告)号：US5832534A
公开(公告)日：1998-11-03
申请号：US550777
申请日：1995-10-31
申请人： Gurbir Singh , Konrad K. Lai , Michael W. Rhodehamel
发明人： Gurbir Singh , Konrad K. Lai , Michael W. Rhodehamel
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0811 , G06F12/0897 , G06F12/0831 , Y02B60/1225
摘要： A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.

3. 发明授权

US5636374A Method and apparatus for performing operations based upon the addresses of microinstructions 失效
标题翻译：基于微指令地址执行操作的方法和装置
公开(公告)号：US5636374A
公开(公告)日：1997-06-03
申请号：US470842
申请日：1995-06-06
申请人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
发明人： Scott D. Rodgers , Keshavan K. Tiruvallur , Michael W. Rhodehamel , Kris G. Konigsfeld , Andrew F. Glew , Haitham Akkary , Milind A. Karnik , James A. Brayton
IPC分类号： G06F9/312 , G06F12/08 , G06F12/10 , G06F9/30
CPC分类号： G06F9/30043 , G06F12/0891 , G06F12/1027
摘要： In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.
摘要翻译：在微处理器中，用于执行存储器功能并发布总线周期的装置和方法。特殊的微指令存储在微码ROM中。这些微指令用于执行存储器功能并产生特殊的总线周期。最初，对于这些特殊微指令之一产生与要执行的请求操作相对应的地址。该特殊微指令及其地址然后通过总线传输到微处理器的各个单元。当每个单元接收微指令时，它根据该地址确定该微指令是否被忽略。如果特定单元忽略微指令，则微指令将转发到管道中的后续单元进行处理。否则，如果该特定单元执行由微指令的地址指定的请求操作。

4. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

5. 发明授权

US5845107A Signaling protocol conversion between a processor and a high-performance system bus 失效
标题翻译：处理器与高性能系统总线之间的信号协议转换
公开(公告)号：US5845107A
公开(公告)日：1998-12-01
申请号：US675679
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F12/08 , G06F13/364 , G06F15/76
CPC分类号： G06F13/364
摘要： A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.
摘要翻译：一种具有主处理器，流水线系统总线和至少一个代理的计算机系统中的操作方法，所有这些代理都按照第一信令协议进行操作，并且处理器包括在根据第二信令协议与第一信令协议不兼容。该方法包括以下步骤：将由子系统处理器产生的仲裁信号从第二信令协议转换为流水线总线的第一信令协议以获得流水线总线的所有权。接下来，将处理器的输出请求编码从第二信令协议转换为第一信令协议。最后，根据流水线总线的第一信令协议从流水线总线生成总线循环，根据翻译的输出请求编码。

6. 发明授权

US5797026A Method and apparatus for self-snooping a bus during a boundary transaction 失效
标题翻译：在边界交易过程中自动侦听总线的方法和装置
公开(公告)号：US5797026A
公开(公告)日：1998-08-18
申请号：US921845
申请日：1997-09-02
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
摘要翻译：一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

7. 发明授权

US5682516A Computer system that maintains system wide cache coherency during deferred communication transactions 失效
标题翻译：计算机系统在延迟通信事务期间维持系统级缓存一致性
公开(公告)号：US5682516A
公开(公告)日：1997-10-28
申请号：US205023
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
IPC分类号： G06F12/08 , G06F13/368 , H04L29/06 , G06F13/18
CPC分类号： G06F12/0831 , G06F13/368 , H04L29/06 , G06F12/0813
摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.
摘要翻译：公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

8. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

9. 发明授权

US5909699A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
标题翻译：用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性
公开(公告)号：US5909699A
公开(公告)日：1999-06-01
申请号：US672422
申请日：1996-06-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
摘要翻译：总线上代理发出的内存请求在保持缓存一致性的同时得到满足。请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。在写请求的情况下，请求代理随着请求传送总线上的写数据。该写入数据由临时存储数据的存储单元和监听代理二者检索。随后，窥探代理通过总线传输整个高速缓存行。存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

10. 发明授权

US5809524A Method and apparatus for cache memory replacement line identification 失效
标题翻译：用于高速缓存存储器替换线路识别的方法和装置
公开(公告)号：US5809524A
公开(公告)日：1998-09-15
申请号：US822044
申请日：1997-03-24
申请人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
发明人： Gurbir Singh , Wen-Hann Wang , Michael W. Rhodehamel , John M. Bauer , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/123 , G06F12/0831
摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.
摘要翻译：一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。该接口包括地址总线，数据总线和状态总线。地址总线将请求的地址从控制器传送到高速缓冲存储器。数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。

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