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1. 发明申请

US20100107037A1 MEMORY SYSTEM WITH ERROR CORRECTION AND METHOD OF OPERATION 有权
标题翻译：具有错误校正的记忆系统和操作方法
公开(公告)号：US20100107037A1
公开(公告)日：2010-04-29
申请号：US12260727
申请日：2008-10-29
申请人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
发明人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064
摘要： A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.
摘要翻译：提供了一种用于存储器的纠错的方法。该方法包括：提供第一存储器和第二存储器; 启动第一存储器的读取操作以检索数据; 对所述数据执行纠错码（ECC）处理，其中所述ECC处理用于确定所述数据的至少一部分是错误的并且用于提供校正数据; 并且确定所述错误数据的地址是否存储在所述第二存储器中，如果所述错误数据的地址被存储在所述第二存储器中，则将所述校正数据存储在所述第二存储器中，并且所述错误数据的地址未被存储在第二存储器中，将地址存储在第二存储器中。

2. 发明申请

US20140321185A1 FOUR PORT MEMORY WITH MULTIPLE CORES 有权
标题翻译：四端口存储器与多个CORES
公开(公告)号：US20140321185A1
公开(公告)日：2014-10-30
申请号：US13873998
申请日：2013-04-30
申请人： Perry H. Pelley , Peter J. Wilson
发明人： Perry H. Pelley , Peter J. Wilson
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/02 , G11C7/1075 , G11C8/16
摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
摘要翻译：存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口，第三个港口和第四个港口。第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

3. 发明授权

US08861243B1 Four port memory with multiple cores 有权
标题翻译：具有多个内核的四端口内存
公开(公告)号：US08861243B1
公开(公告)日：2014-10-14
申请号：US13873998
申请日：2013-04-30
申请人： Perry H. Pelley , Peter J. Wilson
发明人： Perry H. Pelley , Peter J. Wilson
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/02 , G11C7/1075 , G11C8/16
摘要： A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
摘要翻译：存储器簇包括布置成具有中心孔的第一块，第二块，第三块和第四块，其中第一块，第二块，第三块和第四块每个都具有第一端口，第二端口，第三个港口和第四个港口。第一芯在中心孔中，耦合到第一，第二，第三和第四块中的每一个的第一端口。第二芯在与第一，第二，第三和第四块中的每一个的第二端口连接的中心孔中。第三芯在中心孔中，连接到第一，第二，第三和第四块中的每一个的第三端口。中心孔中的第四个核心耦合到第一，第二，第三和第四块中的每一个的第四端口。

4. 发明授权

US08402327B2 Memory system with error correction and method of operation 有权
标题翻译：具有纠错和操作方法的存储系统
公开(公告)号：US08402327B2
公开(公告)日：2013-03-19
申请号：US12260727
申请日：2008-10-29
申请人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
发明人： Perry H. Pelley, III , George P. Hoekstra , Peter J. Wilson
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.
摘要翻译：提供了一种用于存储器的纠错的方法。该方法包括：提供第一存储器和第二存储器; 启动第一存储器的读取操作以检索数据; 对所述数据执行纠错码（ECC）处理，其中所述ECC处理用于确定所述数据的至少一部分是错误的并且用于提供校正数据; 并且确定所述错误数据的地址是否存储在所述第二存储器中，如果所述错误数据的地址被存储在所述第二存储器中，则将所述校正数据存储在所述第二存储器中，并且所述错误数据的地址未被存储在第二存储器中，将地址存储在第二存储器中。

5. 发明授权

US08990546B2 Data processing system with safe call and return 有权
标题翻译：数据处理系统具有安全通话和退货
公开(公告)号：US08990546B2
公开(公告)日：2015-03-24
申请号：US13285434
申请日：2011-10-31
申请人： Peter J. Wilson
发明人： Peter J. Wilson
IPC分类号： G06F9/30 , G06F12/02 , G06F9/44 , G06F12/10
CPC分类号： G06F9/30054 , G06F9/448 , G06F9/4484 , G06F12/02 , G06F12/10
摘要： Embodiments of a system and method are disclosed that can include a memory unit, and a memory management unit coupled to the memory unit. The memory management unit can include address mapping circuitry and access control circuitry operable to: provide address mappings for at least a frame stack and a link stack in the memory unit for programs being executed by the processing unit, and provide an access permission indicator applicable to any segment of the memory unit. A processing unit can save context information for a program to the frame stack, and execute a savelink instruction subsequent to the execution of a branch and link instruction. If the access permission indicator is set, the savelink instruction saves to the link stack a return address provided by the branch and link instruction.
摘要翻译：公开了一种系统和方法的实施例，其可以包括存储器单元和耦合到存储器单元的存储器管理单元。存储器管理单元可以包括地址映射电路和访问控制电路，其可操作以：为存储器单元中的至少一个帧栈和链路堆栈提供用于由处理单元执行的程序的地址映射，并提供适用于存储单元的任何段。处理单元可以将程序的上下文信息保存到帧栈，并且在执行分支和链接指令之后执行搜索指令。如果设置了访问许可指示符，则savelink指令将链路栈中的返回地址保存到链路栈，并返回链路指令。

6. 发明授权

US6032207A Search mechanism for a queue system 失效
标题翻译：队列系统的搜索机制
公开(公告)号：US6032207A
公开(公告)日：2000-02-29
申请号：US994882
申请日：1997-12-19
申请人： Peter J. Wilson
发明人： Peter J. Wilson
IPC分类号： G06F7/24 , G06F17/30 , G06F7/02
CPC分类号： G06F17/30958 , G06F7/24 , Y10S707/99933 , Y10S707/99943
摘要： A search mechanism improves the performance of a queue system including a queue for storing a plurality of data items and search mechanism by maintaining a key cache data structure having an array of entries, each of which have a key field and a pointer field. The key and pointer fields respectively of each cache entry are used for storing a key value of a different one of the enqueued data items of the queue and a pointer to that enqueued item. The key of each data item to be enqueued is used to generate an index value for accessing a location of the key cache array to obtain immediate access to the corresponding enqueued data item thereby reducing the search time for determining the proper point within the queue for inserting the data item to be added.
摘要翻译：搜索机制通过维护具有条目数组的密钥高速缓存数据结构来提高包括用于存储多个数据项和搜索机制的队列的队列系统的性能，每个密钥高速缓存数据结构具有密钥字段和指针字段。每个缓存条目的关键字和指针字段用于存储队列中不同的一个入队数据项和指向该入队项的指针的键值。要排入的每个数据项的密钥用于生成用于访问密钥高速缓存阵列的位置的索引值，以获得对相应的入队数据项的立即访问，从而减少用于确定队列内适当点的搜索时间以插入要添加的数据项。

7. 发明授权

US06541254B1 Glycosylation variants of iduronate 2-sulfatase 有权
标题翻译：糖尿病糖苷酸2-硫酸酯酶的糖基化变体
公开(公告)号：US06541254B1
公开(公告)日：2003-04-01
申请号：US09685844
申请日：2000-10-10
申请人： Peter J. Wilson , Charles Phillip Morris , Donald Stewart Anson , Teresa Occhiodoro , Julie Bielicki , Peter Roy Clements , John Joseph Hopwood
发明人： Peter J. Wilson , Charles Phillip Morris , Donald Stewart Anson , Teresa Occhiodoro , Julie Bielicki , Peter Roy Clements , John Joseph Hopwood
IPC分类号： C12N510
CPC分类号： C12N9/16 , A61K38/00
摘要： The present invention provides a highly glycosylated iduronate-2-sulfatase enzyme comprising an iduronate-2-sulfatase polypeptide with at least 5 kilodalton (kDa) more sugar than iduronate-2-sulfatase purified from a natural source, e.g. human liver. The present invention also provides an enzymatically active polypeptide fragment or variant of such a highly glycosylated iduronate-2-sulfatase. The present invention further provides an isolated nucleic acid encoding iduronate-2-sulfatase, as well as an expression vector, a host cell and a method for producing the present highly glycosylated iduronate-2-sulfatase enzyme. In one embodiment the present invention is directed to a method for producing a glycosylated iduronate-2-sulfatase enzyme which comprises culturing a host cell containing a nucleic acid encoding an enzymatically active iduronate-2-sulfatase polypeptide wherein the host cell glycosylates the polypeptide to a greater degree than a native iduronate-2-sulfatase polypeptide expressed by a natural human liver cell.
摘要翻译：本发明提供了高度糖基化的糖尿病2-硫酸酯酶，其包含与天然来源例如纯化的伊曲膦酸酯-2-硫酸酯酶相比，具有至少5千道尔顿（kDa）多糖的伊万二酸-2-硫酸酯酶多肽。人肝。本发明还提供了这样一种高度糖基化的阿魏酸-2-硫酸酯酶的酶活性多肽片段或变体。本发明还提供了编码艾杜糖醛酸-2-硫酸酯酶的分离的核酸，以及表达载体，宿主细胞和用于制备本发明的高度糖基化的阿拉伯糖酸-2-硫酸酯酶的方法。在一个实施方案中，本发明涉及一种生产糖基化的阿魏酸-2-硫酸酯酶的方法，其包括培养含有编码酶活性的阿魏酸-2-硫酸酯酶多肽的核酸的宿主细胞，其中宿主细胞将多肽糖基化成比由天然人肝细胞表达的天然异二烯酸2-硫酸酯酶多肽更大程度。

8. 发明授权

US4601031A Repairable ROM array 失效
标题翻译：可修复ROM阵列
公开(公告)号：US4601031A
公开(公告)日：1986-07-15
申请号：US545082
申请日：1983-10-24
申请人： Christopher P. H. Walker , Peter J. Wilson
发明人： Christopher P. H. Walker , Peter J. Wilson
IPC分类号： G11C17/00 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10 , G06F11/22
CPC分类号： G11C29/822 , G11C29/846
摘要： The individual rows of a ROM array are accessed by a row decoder/driver in response to the arrival of the address of the individual row on the address lines. A plurality of programmable switches store the address of a row of ROM array found to contain one or more defects. If the incoming address is that of the defective row each of a plurality of comparators connected to both an address line and the associated switch outputs a coincidence signal to an AND gate. The output of the AND gate accesses a spare row of RAM which thus replaces the defective row of the ROM array. Access to the spare row is automatic upon receipt of the address of the defective row. Each column of the ROM array contains a check bit computed from the remaining contents of the respective column, and the data to be stored in the spare row is generated from the remaining contents of the ROM array. At initialization, the generated data which should have been stored in the defective row is written into the spare row.
摘要翻译：响应于地址线上单独行的地址的到达，ROM阵列的各行被行解码器/驱动器访问。多个可编程开关存储发现包含一个或多个缺陷的ROM阵列行的地址。如果输入地址是有缺陷的行，则连接到地址线和相关联的开关的多个比较器中的每一个输出与“和”门的一致信号。与门的输出访问RAM的备用行，从而代替ROM阵列的有缺陷的行。在接收到有缺陷的行的地址时，对备用行的访问是自动的。 ROM阵列的每列包含从各列的剩余内容计算的校验位，并且从ROM阵列的剩余内容生成要存储在备用行中的数据。在初始化时，应该将存储在缺陷行中的生成数据写入备用行。

9. 发明申请

US20150046658A1 CACHE ORGANIZATION AND METHOD 有权
标题翻译：缓存组织和方法
公开(公告)号：US20150046658A1
公开(公告)日：2015-02-12
申请号：US13962429
申请日：2013-08-08
申请人： Peter J. Wilson
发明人： Peter J. Wilson
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.
摘要翻译：提供了具有改进的缓存组织的方法和信息处理系统。能够访问存储器的每个寄存器具有关联的元数据，其包含用于相应高速缓存条目的标签，方式和行以及有效位，允许访问高速缓存中的位置的存储器访问直接到达高速缓存的数据阵列，避免需要查找缓存的标签数组中的地址。当缓存行被驱逐时，引用该行的任何元数据都被标记为无效。通过减少对高速缓存数据阵列中访问数据执行的标签查找的数量，将保存否则将通过执行标签查找而消耗的功率，从而降低信息处理系统的功耗以及实现高速缓存所需的高速缓存区域可以降低期望的性能水平。

10. 发明申请

US20140189244A1 SUPPRESSION OF REDUNDANT CACHE STATUS UPDATES 审中-公开
标题翻译：抑制冗员缓存状态更新
公开(公告)号：US20140189244A1
公开(公告)日：2014-07-03
申请号：US13732533
申请日：2013-01-02
申请人： Brian C. Grayson , David P. Burgess , Peter J. Wilson
发明人： Brian C. Grayson , David P. Burgess , Peter J. Wilson
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0864 , Y02D10/13
摘要： A cache management system employs a replacement policy in a manner that manages redundant accesses to cache elements. The cache management system comprises a cache, a replacement policy state storage and an update control module. The update control module comprises a buffer for storing recent addresses, a comparison unit for comparing a new address with those stored in the recent address buffer, and an update unit which determines whether to update the replacement policy state storage. When an address matches those stored in the recent address buffer, a replacement status update is suppressed.
摘要翻译：缓存管理系统以管理对高速缓存元件的冗余访问的方式采用替换策略。高速缓存管理系统包括高速缓存，替换策略状态存储和更新控制模块。更新控制模块包括用于存储最近地址的缓冲器，用于比较新地址和最近地址缓冲器中存储的地址的比较单元，以及确定是否更新替换策略状态存储的更新单元。当地址与存储在最近地址缓冲区中的地址相匹配时，替换状态更新被抑制。

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