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    • 9. 发明授权
    • Method for monitoring metal ion concentrations in plating baths
    • 监测电镀液中金属离子浓度的方法
    • US4725339A
    • 1988-02-16
    • US579733
    • 1984-02-13
    • Perminder BindraSolomon L. LevineDavid N. Light
    • Perminder BindraSolomon L. LevineDavid N. Light
    • C25D21/14G01N27/48G01N27/49
    • G01N27/48G01N27/49
    • A rotating disk electrode system operates at constant speed in a solution whose metal ion concentration is held constant at multiple concentrations within a range of concentration. The current at the working electrode is recorded, while the potential at the working electrode is swept at a predetermined rate for each of the concentration values. The diffusion limiting current is determined for each of the concentration values. Then the rotating disk electrode system is operated continuously in a metal plating bath whose metal ion concentration can vary. A voltage applied to the working electrode produces a current at the electrode whose magnitude is compared to the values of the previous calibration to determine the current metal ion concentration. Alternatively, a rotating disk electrode system is operated over a range of speeds in a solution whose ion concentration is held constant over a range of concentration. Current at the working electrode is measured for a given electric potential applied to the working electrode. In this way, a calibration relationship between the current at the electrode and the range of metal ion concentrations is established which can be used with current measured in the plating bath under the same conditions as those that established the calibration curve to predict the concentration of the bath.
    • 旋转盘电极系统在浓度范围内以多种浓度保持金属离子浓度的溶液中,以恒定速度运转。 记录工作电极处的电流,同时以每个浓度值以预定的速率扫描工作电极处的电位。 确定每个浓度值的扩散限制电流。 然后旋转盘电极系统在其金属离子浓度可以变化的金属电镀浴中连续操作。 施加到工作电极的电压在电极处产生电流,其电流与先前校正值相比较,以确定当前的金属离子浓度。 或者,旋转盘电极系统在离子浓度在浓度范围内保持恒定的溶液中的速度范围内操作。 对施加到工作电极的给定电位测量工作电极处的电流。 以这种方式,建立了电极电流与金属离子浓度范围之间的校准关系,可以在与建立校正曲线的条件相同的条件下在电镀液中测量的电流使用,以预测电极的浓度 浴。
    • 10. 发明授权
    • Flex laminate package for a parallel processor
    • 用于并行处理器的Flex层压包装
    • US5384690A
    • 1995-01-24
    • US97544
    • 1993-07-27
    • Charles R. DavisThomas P. DuffySteven L. HanakovicHoward L. HeckJohn T. KoliasJohn S. KresgeDavid N. LightAjit K. Trivedi
    • Charles R. DavisThomas P. DuffySteven L. HanakovicHoward L. HeckJohn T. KoliasJohn S. KresgeDavid N. LightAjit K. Trivedi
    • H01R4/26H01R4/58H01R12/61H01R13/66H05K1/00H05K1/03H05K1/14H05K3/00H05K3/32H05K3/46H01R23/68
    • H05K3/4635H01R12/613H01R13/665H05K3/462H01R4/26H01R4/58H05K1/0373H05K1/0393H05K2201/015H05K2201/0154H05K2201/09109H05K2201/09536H05K2201/10159H05K3/328H05K3/4623H05K3/4641Y10S428/901Y10T29/49126Y10T29/49128Y10T29/49179Y10T428/24917
    • Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
    • 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上,在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间,存储器间,处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线,地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上,并且通过Z轴与其它柔性层通信, 轴向电路(通孔和通孔)。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容(可粘合)化学相容的低熔点粘合剂,以及任选的与化学不相容的高熔点掩模 可粘合到)在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压,同时避免在不想层压的区域中层压。