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1. 发明授权

US11525857B2 Method for characterizing fluctuation induced by single particle irradiation in a device and application thereof 有权
公开(公告)号：US11525857B2
公开(公告)日：2022-12-13
申请号：US17744282
申请日：2022-05-13
申请人： Peking University
发明人： Xia An , Zhexuan Ren , Gensong Li , Xing Zhang , Ru Huang
IPC分类号： G01R31/28 , G06F30/367 , G06F119/02
摘要： A method for characterizing a fluctuation induced by single particle irradiation in a device. A plurality of devices varying in size are tested respectively before and after irradiation to obtain threshold voltage distribution, such that a threshold voltage fluctuation induced by irradiation is obtained and used to correct a process fluctuation model, so as to correct a design margin of the devices working under the irradiation.

2. 发明授权

US09525133B2 Resistive random access memory with high uniformity and low power consumption and method for fabricating the same 有权
标题翻译：具有高均匀性和低功耗的电阻式随机存取存储器及其制造方法
公开(公告)号：US09525133B2
公开(公告)日：2016-12-20
申请号：US14916950
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Muxi Yu , Yimao Cai , Zhenxing Zhang , Qiang Li , Ming Li
IPC分类号： H01L29/00 , H01L47/00 , H01L21/336 , H01L45/00
CPC分类号： H01L45/146 , H01L45/08 , H01L45/1233 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.
摘要翻译：公开了一种电阻随机存取存储器，其从底部到顶部的顺序包括基板，绝缘层，底部电极，电阻材料膜和顶部电极，其中电阻材料膜是四层结构，相同的金属氧化物; 并且四层结构中的四层从底部到顶部具有一个接一个地增加大于十次的电阻值，一个接一个地增加的氧浓度和一个接一个地减小的氧浓度。本发明可以通过根据不同的氧浓度将相同金属氧化物的电阻材料膜分成四层来实现每层中的氧空位导电细丝（CF）的完全形成破裂，从而精确地控制电阻值，从而实现了高均匀性的2位存储。

3. 发明授权

US09502310B1 Integration method for a vertical nanowire transistor 有权
标题翻译：垂直纳米线晶体管的集成方法
公开(公告)号：US09502310B1
公开(公告)日：2016-11-22
申请号：US15078789
申请日：2016-03-23
申请人： PEKING UNIVERSITY
发明人： Ming Li , Yuancheng Yang , Gong Chen , Jiewen Fan , Hao Zhang , Ru Huang
IPC分类号： H01L21/00 , H01L21/8238 , H01L29/06 , H01L29/66 , H01L21/02 , H01L21/306 , H01L21/308 , H01L29/08 , H01L21/768
CPC分类号： H01L21/823885 , B82Y10/00 , B82Y40/00 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L29/0676 , H01L29/401 , H01L29/4236 , H01L29/66439 , H01L29/66545 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.
摘要翻译：本发明公开了一种用于集成垂直纳米线晶体管的方法，属于CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件领域。该方法通过组合选择性外延和侧壁上的替换栅，实现了垂直 - 纳米线晶体管的集成。与用于通过蚀刻形成垂直纳米线通道的现有方法相比，可以精确地控制器件沟道的横截面的尺寸和形状，可以提高器件特性的一致性，以及在成形期间的蚀刻损伤可以避免现有方法中的通道，从而可以提高设备性能。

4. 发明申请

US20160133695A1 A METHOD OF INHIBITING LEAKAGE CURRENT OF TUNNELING TRANSISTOR, AND THE CORRESPONDING DEVICE AND A PREPARATION METHOD THEREOF 审中-公开
标题翻译：一种抑制隧道式晶体管泄漏电流的方法及其相关装置及其制备方法
公开(公告)号：US20160133695A1
公开(公告)日：2016-05-12
申请号：US14893870
申请日：2014-01-09
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Qianqian Huang , Chunlei Wu , Jiaxin Wang , Chao Wang , Yangyuan Wang
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L21/265 , H01L21/3213 , H01L21/308 , H01L21/02 , H01L21/266 , H01L29/78 , H01L29/66
CPC分类号： H01L29/0638 , H01L21/02238 , H01L21/26513 , H01L21/266 , H01L21/308 , H01L21/32139 , H01L29/0649 , H01L29/0653 , H01L29/0834 , H01L29/0847 , H01L29/1033 , H01L29/36 , H01L29/66659 , H01L29/7391 , H01L29/7835
摘要： Provided are a method for suppressing a leakage current of a tunnel field-effect transistor (TFET), a corresponding device, and a manufacturing method, related to the field of field-effect transistor logic devices and circuits in CMOS ultra large-scale integration (ULSI). By inserting an insulating layer (7) between a source region (10) and a transistor body below a tunneling junction, and by inserting no insulating layer at a tunneling junction between a source region and a channel, a source/drain direct tunneling leakage current in a small-sized TFET device is effectively suppressed, and a threshold slope is effectively improved. The manufacturing method for the corresponding device is completely compatible with an existing CMOS process.
摘要翻译：提供了一种用于抑制CMOS超大规模集成中的场效应晶体管逻辑器件和电路领域的隧道场效应晶体管（TFET）的漏电流的方法，相应的器件和制造方法（ ULSI）。通过在源极区域（10）和隧道结下方的晶体管体之间插入绝缘层（7），并且通过在源极区域和沟道之间的隧道结处不插入绝缘层，源极/漏极直接隧道漏电流在小型TFET器件中被有效地抑制，并且有效地提高了阈值斜率。相应设备的制造方法与现有的CMOS工艺完全兼容。

5. 发明申请

US20160118245A1 METHOD FOR FABRICATING QUASI-SOI SOURCE/DRAIN FIELD EFFECT TRANSISTOR DEVICE 有权
标题翻译：用于制造准SOI晶体管/漏极场效应晶体管器件的方法
公开(公告)号：US20160118245A1
公开(公告)日：2016-04-28
申请号：US14787261
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Jiewen Fan , Ming Li , Yuancheng Yang , Haoran Xuan , Hanming Wu , Weihai Bu
IPC分类号： H01L21/02 , H01L21/311 , H01L29/66 , H01L21/3105 , H01L29/08 , H01L29/12
CPC分类号： H01L21/02271 , H01L21/31051 , H01L21/31105 , H01L29/0847 , H01L29/12 , H01L29/165 , H01L29/66477 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing CMOS process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-SOI source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced.
摘要翻译：本发明公开了一种制造准SOI源极/漏极场效应晶体管器件的方法，其特征在于包括以下步骤：形成器件的有源区; 形成该装置的栅堆叠结构; 掺杂源极/漏极延伸区域，以及在栅极堆叠结构的两侧形成第一层侧壁; 形成凹陷的源极/漏极结构; 形成准SOI源极/漏极隔离层; 原位掺杂外延第二半导体材料源极/漏极，并通过退火激活; 如果采用后门处理，则去除先前的虚拟栅极并重新沉积高k金属栅极; 并形成接触和金属互连。本发明的方法与现有的CMOS工艺具有很好的兼容性，具有工艺简单，热量预算小的特点; 并且与传统的场效应晶体管相比，通过根据本发明的方法制造的准SOI源极/漏极场效应晶体管器件，可以有效降低漏电流，从而可以使器件的功耗减少

6. 发明申请

US20160043220A1 TUNNELING FIELD EFFECT TRANSISTOR HAVING A THREE-SIDE SOURCE AND FABRICATION METHOD THEREOF 有权
标题翻译：具有三相源的隧道场效应晶体管及其制造方法
公开(公告)号：US20160043220A1
公开(公告)日：2016-02-11
申请号：US14782284
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Qianqian Huang , Chunlei Wu , Jiaxin Wang , Yangyuan Wang
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L21/266 , H01L21/027 , H01L21/324 , H01L21/308 , H01L21/02 , H01L21/3213 , H01L29/66 , H01L29/08 , H01L21/265
CPC分类号： H01L29/7835 , H01L21/02636 , H01L21/0274 , H01L21/26513 , H01L21/266 , H01L21/28238 , H01L21/308 , H01L21/32139 , H01L21/324 , H01L29/0653 , H01L29/0692 , H01L29/08 , H01L29/0847 , H01L29/1033 , H01L29/165 , H01L29/205 , H01L29/225 , H01L29/267 , H01L29/66356 , H01L29/66659 , H01L29/66977 , H01L29/7391
摘要： The present invention discloses a tunneling field effect transistor having a three-side source and a fabrication method thereof, referring to field effect transistor logic devices and circuits in CMOS ultra large scale integrated circuits (ULSI). By means of the strong depletion effect of the three-side source, the transistor can equivalently achieve a steep doping concentration gradient for the source junction, significantly optimizing the sub-threshold slope of the TFET. Meanwhile, the turn-on current of the transistor is boosted. Furthermore, due to a region uncovered by the gate between the gate and the drain, the bipolar conduction effect of the transistor is effectively inhibited, and on the other hand, in the small-size transistor a parasitic tunneling current at the corner of the source junction is inhibited. The fabrication method is simple and can be accurately controlled. By forming the channel region using an epitaxy method subsequent to etching, it facilitates to form a steeper doping concentration gradient for the source region or form a hetero-junction. Moreover, the fabrication flow of the post-gate process facilitates to integrate a high-k gate dielectric/a metal gate having good quality, further improving the performance of the transistor.
摘要翻译：本发明公开了一种具有三面源的隧道场效应晶体管及其制造方法，参考CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件和电路。通过三侧源的强消耗效应，晶体管可以等效地实现源极结的陡峭掺杂浓度梯度，显着优化了TFET的次阈值斜率。同时，提高了晶体管的导通电流。此外，由于栅极和漏极之间的栅极未覆盖的区域，晶体管的双极导电效应被有效地抑制，另一方面，在小尺寸晶体管中，源极的角落处的寄生隧穿电流结被抑制。制作方法简单，可以精确控制。通过在蚀刻之后使用外延法形成沟道区，有助于形成源区的更陡的掺杂浓度梯度或形成异质结。此外，栅极后工艺的制造流程有助于集成具有良好质量的高k栅极电介质/金属栅极，进一步提高晶体管的性能。

7. 发明申请

US20160020306A1 Short-Gate Tunneling Field Effect Transistor Having Non-Uniformly Doped Vertical Channel and Fabrication Method Thereof 有权
标题翻译：具有非均匀掺杂垂直沟道的短栅隧道场效应晶体管及其制作方法
公开(公告)号：US20160020306A1
公开(公告)日：2016-01-21
申请号：US14771627
申请日：2013-09-30
申请人： Peking University
发明人： Ru Huang , Chunlei Wu , Qianqian Huang , Chao Wang , Jiaxin Wang , Yangyuan Wang
IPC分类号： H01L29/66 , H01L29/423 , H01L29/08 , H01L29/10 , H01L21/266 , H01L29/06 , H01L29/51 , H01L29/49 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66977 , B82Y10/00 , H01L21/266 , H01L21/28194 , H01L21/28202 , H01L29/0649 , H01L29/0676 , H01L29/0847 , H01L29/1041 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/401 , H01L29/413 , H01L29/41775 , H01L29/42376 , H01L29/4916 , H01L29/495 , H01L29/51 , H01L29/518 , H01L29/66356 , H01L29/66439 , H01L29/66484 , H01L29/66666 , H01L29/7391 , H01L29/7827 , H01L29/7831
摘要： The present invention discloses a short-gate tunneling field effect transistor having a non-uniformly doped vertical channel and a fabrication method thereof. The short-gate tunneling field effect transistor has a vertical channel and the channel region is doped in such a slowly-varied and non-uniform manner that a doping concentration in the channel region appears a Gaussian distribution along a vertical direction and the doping concentration in the channel near the drain region is higher while the doping concentration in the channel near the source region is lower; and double control gates are formed at both sides of the vertical channel and the control gates form an L-shaped short-gate structure, so that a gate underlapped region is formed in the channel near the drain region, and a gate overlapped region is formed at the source region. As compared with a conventional TFET, the short-gate tunneling field effect transistor according to the present invention can effectively suppress the impact of the electrical field at the drain region on the tunneling width of the tunneling junction at the source region; the super exponential relationship between the output tunneling current and the drain voltage is weakened; and the output characteristic of the transistor is significantly improved. Meanwhile, the tunneling field effect transistor is beneficial to increase the on-current of the transistor and to gain a steeper sub-threshold slope.
摘要翻译：本发明公开了一种具有非均匀掺杂垂直沟道的短栅隧道场效应晶体管及其制造方法。短栅隧道场效应晶体管具有垂直沟道，并且以如此缓慢变化和不均匀的方式掺杂沟道区，使得沟道区中的掺杂浓度出现沿着垂直方向的高斯分布，并且掺杂浓度靠近漏极区的沟道较高，而源区附近的沟道中的掺杂浓度较低; 并且在垂直沟道的两侧形成双重控制栅极，并且控制栅极形成L形的短栅极结构，使得在漏极区域附近的沟道中形成栅极重叠区域，并且形成栅极重叠区域在源地区。与常规TFET相比，根据本发明的短栅隧穿场效应晶体管可以有效地抑制漏极区电场对源极区隧道结的隧道宽度的影响; 输出隧穿电流与漏极电压之间的超指数关系减弱; 晶体管的输出特性显着提高。同时，隧道场效应晶体管有利于增加晶体管的导通电流并获得更陡的子阈值斜率。

8. 发明申请

US20150236130A1 METHOD FOR FABRICATING FINFET WITH SEPARATED DOUBLE GATES ON BULK SILICON 有权
标题翻译：用于制造具有分开的双层硅的FINFET的方法
公开(公告)号：US20150236130A1
公开(公告)日：2015-08-20
申请号：US14006219
申请日：2012-10-11
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Jiewen Fan , Xiaoyan Xu , Jia Li , Runsheng Wang
IPC分类号： H01L29/66 , H01L21/027 , H01L21/311 , H01L21/306 , H01L29/06 , H01L21/321 , H01L21/3213 , H01L21/265 , H01L21/324 , H01L21/02 , H01L21/28
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02255 , H01L21/0277 , H01L21/26513 , H01L21/28035 , H01L21/30604 , H01L21/31116 , H01L21/3212 , H01L21/32133 , H01L21/324 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/0649
摘要： Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed. Further, the power consumption of the device can be further reduced through the special multi-threshold characteristic of the device with separated double gates.
摘要翻译：本文公开了一种用于在体硅上制造具有分离的双栅极的FinFET的方法，包括：形成源极，漏极和连接源极和漏极的薄条的图案; 形成氧化隔离层; 形成栅极结构和源极/漏极结构; 并形成金属接触和金属互连。通过本文的方法，在体硅晶片上制造具有分离的双栅极的FinFET非常容易，并且整个工艺流程与传统的基于硅的超大规模集成电路制造技术完全兼容。因此，本方法简单，方便，工艺时间短，大大节约了硅片的成本。此外，通过使用通过根据本发明的方法制造的分离的双栅极的FinFET，可以有效地抑制短沟道效应。此外，通过具有分离的双门的器件的特殊的多阈值特性，可以进一步降低器件的功耗。

9. 发明申请

US20140220748A1 METHOD FOR FABRICATING COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR BASED ON STANDARD CMOS IC PROCESS 有权
标题翻译：基于标准CMOS IC工艺制作补充性隧道效应晶体管的方法
公开(公告)号：US20140220748A1
公开(公告)日：2014-08-07
申请号：US13884095
申请日：2012-06-14
申请人： Peking University
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/823814 , H01L29/66356 , H01L29/7391
摘要： Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.
摘要翻译：本文公开了一种用于制造基于标准CMOS IC工艺的互补隧道场效应晶体管的方法，其属于超大规模集成（ULSI）电路中的场效应晶体管的逻辑器件和电路领域。在该方法中，TFET的本征通道和体区通过在标准CMOS IC工艺中的互补P阱和N阱掩模形成，以形成阱掺杂，沟道掺杂和通过注入进行阈值调整。此外，可以通过布局上的栅极和漏极之间的距离来抑制TFET中的双极效应，从而形成互补的TFET。在根据本发明的方法中，互补隧穿场效应晶体管（TFET）可以通过标准CMOS IC工艺中的现有工艺制造而无需任何附加的掩模和工艺步骤。

10. 发明授权

US12000792B2 CMOS-MEMS humidity sensor 有权
公开(公告)号：US12000792B2
公开(公告)日：2024-06-04
申请号：US17621977
申请日：2020-06-30
申请人： HANGZHOU WEIMING XINKE TECHNOLOGY CO., LTD , ADVANCED INSTITUTE OF INFORMATION TECHNOLOGY (AIIT) , PEKING UNIVERSITY
发明人： Han Xiao , Guangjun Yu , Le Ye , Ru Huang
IPC分类号： G01N27/22 , B81B7/00
CPC分类号： G01N27/223 , B81B7/0096 , B81B2201/0214 , B81B2203/0136 , B81B2203/04 , B81B2207/015
摘要： A CMOS-MEMS humidity sensor includes a complementary metal oxide semiconductor (CMOS) ASIC readout circuit and a microelectromechanical system (MEMS) humidity sensor. The MEMS humidity sensor is provided on the ASIC readout circuit. The ASIC readout circuit includes a substrate, a heating resistor layer located above the substrate, a metal layer located above the heating resistor layer, and dielectric layers. The substrate, the heating resistor layer, and the metal layer are partitioned by dielectric layers. The MEMS humidity sensor includes an aluminum electrode layer, a passivation layer located above the aluminum electrode layer, and a humidity sensitive layer located above the passivation layer. The provision of heating resistors in the ASIC circuit realizes the heating function and satisfies the requirements of the standard CMOS process, so that the CMOS-MEMS integrated humidity sensor can be used stably under low temperature and high humidity conditions.

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