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1. 发明授权

US09525133B2 Resistive random access memory with high uniformity and low power consumption and method for fabricating the same 有权
标题翻译：具有高均匀性和低功耗的电阻式随机存取存储器及其制造方法
公开(公告)号：US09525133B2
公开(公告)日：2016-12-20
申请号：US14916950
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Muxi Yu , Yimao Cai , Zhenxing Zhang , Qiang Li , Ming Li
IPC分类号： H01L29/00 , H01L47/00 , H01L21/336 , H01L45/00
CPC分类号： H01L45/146 , H01L45/08 , H01L45/1233 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要： Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.
摘要翻译：公开了一种电阻随机存取存储器，其从底部到顶部的顺序包括基板，绝缘层，底部电极，电阻材料膜和顶部电极，其中电阻材料膜是四层结构，相同的金属氧化物; 并且四层结构中的四层从底部到顶部具有一个接一个地增加大于十次的电阻值，一个接一个地增加的氧浓度和一个接一个地减小的氧浓度。本发明可以通过根据不同的氧浓度将相同金属氧化物的电阻材料膜分成四层来实现每层中的氧空位导电细丝（CF）的完全形成破裂，从而精确地控制电阻值，从而实现了高均匀性的2位存储。

2. 发明授权

US09502310B1 Integration method for a vertical nanowire transistor 有权
标题翻译：垂直纳米线晶体管的集成方法
公开(公告)号：US09502310B1
公开(公告)日：2016-11-22
申请号：US15078789
申请日：2016-03-23
申请人： PEKING UNIVERSITY
发明人： Ming Li , Yuancheng Yang , Gong Chen , Jiewen Fan , Hao Zhang , Ru Huang
IPC分类号： H01L21/00 , H01L21/8238 , H01L29/06 , H01L29/66 , H01L21/02 , H01L21/306 , H01L21/308 , H01L29/08 , H01L21/768
CPC分类号： H01L21/823885 , B82Y10/00 , B82Y40/00 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871 , H01L21/823878 , H01L29/0676 , H01L29/401 , H01L29/4236 , H01L29/66439 , H01L29/66545 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.
摘要翻译：本发明公开了一种用于集成垂直纳米线晶体管的方法，属于CMOS超大规模集成电路（ULSI）中的场效应晶体管逻辑器件领域。该方法通过组合选择性外延和侧壁上的替换栅，实现了垂直 - 纳米线晶体管的集成。与用于通过蚀刻形成垂直纳米线通道的现有方法相比，可以精确地控制器件沟道的横截面的尺寸和形状，可以提高器件特性的一致性，以及在成形期间的蚀刻损伤可以避免现有方法中的通道，从而可以提高设备性能。

3. 发明申请

US20160118245A1 METHOD FOR FABRICATING QUASI-SOI SOURCE/DRAIN FIELD EFFECT TRANSISTOR DEVICE 有权
标题翻译：用于制造准SOI晶体管/漏极场效应晶体管器件的方法
公开(公告)号：US20160118245A1
公开(公告)日：2016-04-28
申请号：US14787261
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Jiewen Fan , Ming Li , Yuancheng Yang , Haoran Xuan , Hanming Wu , Weihai Bu
IPC分类号： H01L21/02 , H01L21/311 , H01L29/66 , H01L21/3105 , H01L29/08 , H01L29/12
CPC分类号： H01L21/02271 , H01L21/31051 , H01L21/31105 , H01L29/0847 , H01L29/12 , H01L29/165 , H01L29/66477 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing CMOS process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-SOI source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced.
摘要翻译：本发明公开了一种制造准SOI源极/漏极场效应晶体管器件的方法，其特征在于包括以下步骤：形成器件的有源区; 形成该装置的栅堆叠结构; 掺杂源极/漏极延伸区域，以及在栅极堆叠结构的两侧形成第一层侧壁; 形成凹陷的源极/漏极结构; 形成准SOI源极/漏极隔离层; 原位掺杂外延第二半导体材料源极/漏极，并通过退火激活; 如果采用后门处理，则去除先前的虚拟栅极并重新沉积高k金属栅极; 并形成接触和金属互连。本发明的方法与现有的CMOS工艺具有很好的兼容性，具有工艺简单，热量预算小的特点; 并且与传统的场效应晶体管相比，通过根据本发明的方法制造的准SOI源极/漏极场效应晶体管器件，可以有效降低漏电流，从而可以使器件的功耗减少

4. 发明授权

US09484208B2 Preparation method of a germanium-based schottky junction 有权
标题翻译：锗基肖特基结的制备方法
公开(公告)号：US09484208B2
公开(公告)日：2016-11-01
申请号：US14380026
申请日：2013-09-30
申请人： Peking University
发明人： Ru Huang , Meng Lin , Zhiqiang Li , Xia An , Ming Li , Quanxin Yun , Min Li , Pengqiang Liu , Xing Zhang
IPC分类号： H01L21/28 , H01L21/285 , H01L29/812 , H01L29/66 , H01L29/80 , H01L29/872 , H01L21/02 , H01L21/3213
CPC分类号： H01L21/28537 , H01L21/02052 , H01L21/02192 , H01L21/02266 , H01L21/02271 , H01L21/0228 , H01L21/28568 , H01L21/3213 , H01L29/66143 , H01L29/66848 , H01L29/806 , H01L29/812 , H01L29/872
摘要： The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.
摘要翻译：本发明公开了一种基于锗的肖特基结的制备方法，包括：清洗N型锗基基材的表面，然后在表面上沉积一层CeO 2，并进一步沉积一层金属。稀土氧化物CeO2与锗衬底接触后，Ce-O-Ge键的稳定性可以在界面形成，有利于降低界面态密度，提高界面质量，降低MIGS和抑制费米级钉扎。同时，与Si3N4，Al2O3，Ge3N4等的情况相比，金属和锗衬底之间的CeO 2引入的隧穿电阻较小。鉴于相对于锗衬底的优异的表面特性和较小的导带偏移，CeO 2电介质层的插入适用于制备具有低电阻率的锗基肖特基结。

5. 发明申请

US20160181114A1 Method for Fabricating Multiple Layers of Ultra Narrow Silicon Wires 有权
标题翻译：制造多层超窄导线的方法
公开(公告)号：US20160181114A1
公开(公告)日：2016-06-23
申请号：US14907371
申请日：2014-03-28
申请人： PEKING UNIVERSITY
发明人： Ming Li , Yuancheng Yang , Jiewen Fan , Haoran Xuan , Hao Zhang , Ru Huang
IPC分类号： H01L21/308 , H01L21/306 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/02 , H01L29/04
CPC分类号： H01L21/3088 , B82Y10/00 , H01L21/02532 , H01L21/02603 , H01L21/02609 , H01L21/30608 , H01L21/30625 , H01L21/3081 , H01L21/3085 , H01L21/3086 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/775 , H01L29/78654 , H01L29/78696
摘要： A method for preparing a multilayer superfine silicon line, comprising: preparing an etching masking layer of silicon; forming a fin and source/drain region on both ends thereof by epitaxy; and forming a multilayer superfine silicon line. The method has the following advantages: the atom layer deposition accurately defines the position of the superfine line, giving good controllability; the anisotropic etching of the silicon is automatically stopped, so the process window is large, and the cross section of a nanowire obtained via etching is uniform and flat; a method of mask preparation before channel epitaxy is employed to provide a simple process of forming a multilayer sidewall etching mask, i.e., the multilayer sidewall mask is obtained by etching an epitaxial window only once irrespective of the number of masking layers; a line having a size less than 10 nm can be prepared in conjunction with oxidation technology, thus satisfying the requirement of the key process of a small-sized device. Polycrystalline silicon can be etched by employing a TMAH solution wet process, being simple, convenient and safe, without introducing metal, thus being suitable for the manufacturing process of an integrated circuit; and the method is completely compatible with a bulk silicon planar transistor process, thus having small process costs.
摘要翻译：一种制备多层超细硅线的方法，包括：制备硅的蚀刻掩模层; 通过外延在其两端形成鳍和源极/漏极区; 并形成多层超细硅线。该方法具有以下优点：原子层沉积精确定义超细线的位置，具有良好的可控性; 硅的各向异性蚀刻自动停止，因此工艺窗口大，通过蚀刻获得的纳米线的横截面均匀且平坦; 使用通道外延之前的掩模制备方法来提供形成多层侧壁蚀刻掩模的简单工艺，即多层侧壁掩模是通过仅对掩模层的数量进行蚀刻外延窗而获得的; 可以结合氧化技术制备尺寸小于10nm的线，从而满足小尺寸器件的关键过程的要求。可以通过采用TMAH溶液湿法蚀刻多晶硅，简单，方便，安全，不引入金属，因此适用于集成电路的制造工艺; 并且该方法与体硅平面晶体管工艺完全兼容，因此具有小的工艺成本。

6. 发明授权

US09356124B2 Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure 有权
标题翻译：制造具有准SOI结构的源极和漏极的多栅极结构器件的方法
公开(公告)号：US09356124B2
公开(公告)日：2016-05-31
申请号：US14764155
申请日：2013-09-30
申请人： Peking University
发明人： Ru Huang , Jiewen Fan , Jia Li , Xiaoyan Xu , Ming Li
IPC分类号： H01L21/00 , H01L29/66 , H01L21/02 , H01L21/311 , H01L21/762 , H01L21/3105 , H01L21/265 , H01L21/324 , H01L21/3065 , H01L29/08 , H01L21/28 , H01L21/285 , H01L29/51 , H01L21/321
CPC分类号： H01L29/66795 , H01L21/02164 , H01L21/0217 , H01L21/02181 , H01L21/0228 , H01L21/26513 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/3065 , H01L21/31055 , H01L21/31116 , H01L21/3212 , H01L21/324 , H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66575 , H01L29/7851
摘要： A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.
摘要翻译：一种用于制造具有准SOI结构的源极和漏极的多栅极结构器件的方法，包括形成鳍状形状的有源区，形成用于浅沟槽隔离（STI）的氧化物隔离层，形成多晶硅虚拟栅极，形成源极和漏极延伸区域，形成具有准SOI结构的源极和漏极，并形成高K金属栅极。可以通过使用与常规体硅CMOS工艺兼容的工艺方法来实现与本发明一致的解决方案，并且可以容易地集成到工艺流程中。此外，即使在具有短的通道长度的情况下，这里的创新也可以提供小的漏电流，从而降低器件的功耗。

7. 发明申请

US20150206752A1 METHOD OF ADJUSTING A THRESHOLD VOLTAGE OF A MULTI-GATE STRUCTURE DEVICE 有权
标题翻译：调节多门结构器件的阈值电压的方法
公开(公告)号：US20150206752A1
公开(公告)日：2015-07-23
申请号：US14415570
申请日：2013-09-30
申请人： Peking University
发明人： Ming Li , Jiewen Fan , Jia Li , Xiaoyan Xu , Ru Huang
IPC分类号： H01L21/225 , H01L29/78 , H01L29/10
CPC分类号： H01L21/2252 , H01L21/00 , H01L29/0673 , H01L29/105 , H01L29/66795 , H01L29/775 , H01L29/7855
摘要： The present invention discloses a method of adjusting a threshold voltage of a multi-gate structure device, wherein, preparing the multi-gate structure device to be formed to have a channel impurity distribution with high doping on surface and lowly doping inside, where while a threshold voltage is adjusted by using impurity doping, the influences of the Coulomb impurity scattering on the carriers is reduced as much as possible, so that the mobility of the carriers is maintained at a higher level. Firstly, the present solution is able to make a multi-gate device obtain a larger range of a multi-threshold voltage; it is convenient for the various demands of the device in the circuit designing by IC designers. Secondly, in the course of introducing the impurity doping to adjust a threshold voltage, the influences of the Coulomb impurity scattering on the channel carrier are reduced as much as possible, so that the mobility of the charge carriers is maintained at a higher level, and the device is ensured to have a higher drive current. Finally, the present solution is achieved by the process method compatible with a conventional CMOS, and has the potential for a large scale production.
摘要翻译：本发明公开了一种调整多栅极结构器件的阈值电压的方法，其中制备要形成的多栅极结构器件具有在表面上具有高掺杂的沟道杂质分布并且内部低掺杂，其中，通过使用杂质掺杂调节阈值电压，尽可能地减少库仑杂质散射对载流子的影响，使得载流子的迁移率保持在更高的水平。首先，本解决方案能够使多栅极器件获得更大范围的多阈值电压; 在IC设计人员的电路设计中，对设备的各种需求是方便的。其次，在引入杂质掺杂以调整阈值电压的过程中，尽可能地减少库仑杂质散射对沟道载流子的影响，使得载流子的迁移率保持在更高的水平，并且该装置被确保具有较高的驱动电流。最后，本解决方案通过与常规CMOS兼容的工艺方法实现，并且具有大规模生产的潜力。

8. 发明授权

US09396949B2 Method of adjusting a threshold voltage of a multi-gate structure device 有权
标题翻译：调整多栅极结构器件的阈值电压的方法
公开(公告)号：US09396949B2
公开(公告)日：2016-07-19
申请号：US14415570
申请日：2013-09-30
申请人： Peking University
发明人： Ming Li , Jiewen Fan , Jia Li , Xiaoyan Xu , Ru Huang
IPC分类号： H01L21/225 , H01L21/00 , H01L29/06 , H01L29/66 , H01L29/10 , H01L29/78 , H01L29/775
CPC分类号： H01L21/2252 , H01L21/00 , H01L29/0673 , H01L29/105 , H01L29/66795 , H01L29/775 , H01L29/7855
摘要： The present invention discloses a method of adjusting a threshold voltage of a multi-gate structure device, wherein, preparing the multi-gate structure device to be formed to have a channel impurity distribution with high doping on surface and lowly doping inside, where while a threshold voltage is adjusted by using impurity doping, the influences of the Coulomb impurity scattering on the carriers is reduced as much as possible, so that the mobility of the carriers is maintained at a higher level. Firstly, the present solution is able to make a multi-gate device obtain a larger range of a multi-threshold voltage; it is convenient for the various demands of the device in the circuit designing by IC designers. Secondly, in the course of introducing the impurity doping to adjust a threshold voltage, the influences of the Coulomb impurity scattering on the channel carrier are reduced as much as possible, so that the mobility of the charge carriers is maintained at a higher level, and the device is ensured to have a higher drive current. Finally, the present solution is achieved by the process method compatible with a conventional CMOS, and has the potential for a large scale production.
摘要翻译：本发明公开了一种调整多栅极结构器件的阈值电压的方法，其中制备要形成的多栅极结构器件具有在表面上具有高掺杂的沟道杂质分布并且内部低掺杂，其中，通过使用杂质掺杂调节阈值电压，尽可能地减少库仑杂质散射对载流子的影响，使得载流子的迁移率保持在更高的水平。首先，本解决方案能够使多栅极器件获得更大范围的多阈值电压; 在IC设计人员的电路设计中，对设备的各种需求是方便的。其次，在引入杂质掺杂以调整阈值电压的过程中，尽可能地减少库仑杂质散射对沟道载流子的影响，使得载流子的迁移率保持在更高的水平，并且该装置被确保具有较高的驱动电流。最后，本解决方案通过与常规CMOS兼容的工艺方法实现，并且具有大规模生产的潜力。

9. 发明授权

US09349588B2 Method for fabricating quasi-SOI source/drain field effect transistor device 有权
标题翻译：准SOI源/漏场效应晶体管器件的制造方法
公开(公告)号：US09349588B2
公开(公告)日：2016-05-24
申请号：US14787261
申请日：2014-03-31
申请人： PEKING UNIVERSITY
发明人： Ru Huang , Jiewen Fan , Ming Li , Yuancheng Yang , Haoran Xuan , Hanming Wu , Weihai Bu
IPC分类号： H01L21/00 , H01L21/02 , H01L29/08 , H01L29/12 , H01L29/66 , H01L21/3105 , H01L21/311
CPC分类号： H01L21/02271 , H01L21/31051 , H01L21/31105 , H01L29/0847 , H01L29/12 , H01L29/165 , H01L29/66477 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/7834
摘要： The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections. The method of the invention is well compatible with the existing CMOS process, and it has the features of simple process and small heat budget; and in comparison with the traditional field effect transistor, by means of the quasi-SOI source/drain field effect transistor device fabricated according to the method of the invention, the leakage current can be lowered effectively, thus the power consumption of the device can be reduced.
摘要翻译：本发明公开了一种制造准SOI源极/漏极场效应晶体管器件的方法，其特征在于包括以下步骤：形成器件的有源区; 形成该装置的栅堆叠结构; 掺杂源极/漏极延伸区域，以及在栅极堆叠结构的两侧形成第一层侧壁; 形成凹陷的源极/漏极结构; 形成准SOI源极/漏极隔离层; 原位掺杂外延第二半导体材料源极/漏极，并通过退火激活; 如果采用后门处理，则去除先前的虚拟栅极并重新沉积高k金属栅极; 并形成接触和金属互连。本发明的方法与现有的CMOS工艺具有很好的兼容性，具有工艺简单，热量预算小的特点; 并且与传统的场效应晶体管相比，通过根据本发明的方法制造的准SOI源极/漏极场效应晶体管器件，可以有效降低漏电流，从而可以使器件的功耗减少

10. 发明申请

US20160133475A1 PREPARATION METHOD OF A GERMANIUM-BASED SCHOTTKY JUNCTION 有权
标题翻译：基于锗的肖特基结的制备方法
公开(公告)号：US20160133475A1
公开(公告)日：2016-05-12
申请号：US14380026
申请日：2013-09-30
申请人： Peking University
发明人： Ru Huang , Meng Lin , Zhiqiang Li , Xia An , Ming Li , Quanxin Yun , Min Li , Pengqiang Liu , Xing Zhang
IPC分类号： H01L21/285 , H01L21/3213 , H01L21/02
CPC分类号： H01L21/28537 , H01L21/02052 , H01L21/02192 , H01L21/02266 , H01L21/02271 , H01L21/0228 , H01L21/28568 , H01L21/3213 , H01L29/66143 , H01L29/66848 , H01L29/806 , H01L29/812 , H01L29/872
摘要： The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO2 between the metal and the germanium substrate is smaller relative to the case of Si3N4, Al2O3, Ge3N4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.
摘要翻译：本发明公开了一种基于锗的肖特基结的制备方法，包括：清洗N型锗基基材的表面，然后在表面上沉积一层CeO 2，并进一步沉积一层金属。稀土氧化物CeO2与锗衬底接触后，Ce-O-Ge键的稳定性可以在界面形成，有利于降低界面态密度，提高界面质量，降低MIGS和抑制费米级钉扎。同时，与Si3N4，Al2O3，Ge3N4等的情况相比，金属和锗衬底之间的CeO2引入的隧穿电阻较小。鉴于相对于锗衬底的优异的表面特性和较小的导带偏移，CeO 2电介质层的插入适用于制备具有低电阻率的锗基肖特基结。

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