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1. 发明授权

US07415581B2 Semiconductor memory chip 失效
标题翻译：半导体存储芯片
公开(公告)号：US07415581B2
公开(公告)日：2008-08-19
申请号：US11242149
申请日：2005-10-04
申请人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmölz
发明人： Paul Wallner , Yukio Fukuzo , Christian Sichert , Paul Schmölz
IPC分类号： G11C7/08 , G11C11/4063
CPC分类号： G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.
摘要翻译：信号作为串行信号帧传送的半导体存储器芯片包括提供存储器核心和接收接口之间的接口的帧解码器。帧解码器包括用于根据解码的命令类型对包括在帧中的命令的类型进行解码的命令类型解码器，用于调度和准备用于核心的单个命令的存储器命令评估器/生成器，中间数据缓冲器命令评估器/生成器用于调度和准备中间数据缓冲器的控制信号，以及用于准备和调度系统命令的系统命令评估器/发生器。这些系统命令提供定时参数，以确保一帧内或帧之间的连续命令之间的时间间隔，并存储在系统模式寄存器中。帧解码器的操作由帧时钟或同步解码器时钟信号进行边沿同步，该时钟信号与该帧时钟信号相对齐。

2. 发明授权

US06922764B2 Memory, processor system and method for performing write operations on a memory region 有权
标题翻译：用于对存储器区域执行写入操作的存储器，处理器系统和方法
公开(公告)号：US06922764B2
公开(公告)日：2005-07-26
申请号：US10299750
申请日：2002-11-19
申请人： Jean-Marc Dortu , Robert Feurle , Paul Schmölz , Andreas Täuber
发明人： Jean-Marc Dortu , Robert Feurle , Paul Schmölz , Andreas Täuber
IPC分类号： G11C7/10 , G06F12/00
CPC分类号： G11C7/1006 , G11C2207/229
摘要： A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit for receiving a data block from the plurality of temporally sequential data bundle data blocks which is to be written into the memory region in dependence on the data mask signal. The memory also includes a unit for writing the received data block into the memory region.
摘要翻译：提供了一种存储器，其具有用于存储数据的存储区域，用于接收具有多个时间顺序数据块的数据束的输入端和用于接收分配给数据束的数据掩码信号的输入端。存储器还具有一个单元，用于根据数据掩码信号从要被写入存储器区域的多个时间上顺序的数据束数据块接收数据块。存储器还包括用于将接收的数据块写入存储器区域的单元。

3. 发明授权

US06646908B2 Integrated memory chip with a dynamic memory 有权
公开(公告)号：US06646908B2
公开(公告)日：2003-11-11
申请号：US10113415
申请日：2002-04-01
申请人： Andreas Täuber , Robert Feurle , Paul Schmölz , Jean-Marc Dortu
发明人： Andreas Täuber , Robert Feurle , Paul Schmölz , Jean-Marc Dortu
IPC分类号： G11C1124
CPC分类号： G11C7/1006 , G11C11/4093
摘要： The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.

4. 发明授权

US06751140B2 Method for testing integrated semiconductor memory devices 失效
标题翻译：集成半导体存储器件的测试方法
公开(公告)号：US06751140B2
公开(公告)日：2004-06-15
申请号：US10245626
申请日：2002-09-17
申请人： Paul Schmölz , Wolfgang Spirkl
发明人： Paul Schmölz , Wolfgang Spirkl
IPC分类号： G11C700
CPC分类号： G11C29/44 , G11C29/48 , G11C29/70
摘要： In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.
摘要翻译：为了能够特别快速地进行集成半导体存储器件的测试，提出了在半导体存储器件的区域中获得的各个存储区域的测试结果数据被形成，发送和/或存储在每种情况下，作为多个块状测试结果列表。

5. 发明授权

US06628553B2 Data output interface, in particular for semiconductor memories 有权
公开(公告)号：US06628553B2
公开(公告)日：2003-09-30
申请号：US10157726
申请日：2002-05-29
申请人： Robert Feurle , Paul Schmölz , Jean-Marc Dortu , Andreas Täuber
发明人： Robert Feurle , Paul Schmölz , Jean-Marc Dortu , Andreas Täuber
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066
摘要： A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

6. 发明授权

US07177999B2 Reading extended data burst from memory 有权
标题翻译：从内存读取扩展数据突发
公开(公告)号：US07177999B2
公开(公告)日：2007-02-13
申请号：US10425002
申请日：2003-04-28
申请人： Andreas Täuber , Paul Schmölz
发明人： Andreas Täuber , Paul Schmölz
IPC分类号： G06F12/00
CPC分类号： G11C7/1027
摘要： A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.
摘要翻译：从半导体存储器读取数据突发长度大于2的数据的方法包括从第一时间开始在地址总线上接收与要寻址的存储器单元相关联的第一地址部分。在比第一次晚的第二时间，在命令总线上放置读取命令以启动对第一存储器单元的读取访问，并且在地址总线上接收与要寻址的存储器单元相关联的第二地址部分。从第二次开始的第三次开始，与第一和第二地址部分相关联的数据被传送到数据总线。

7. 发明授权

US06781220B2 Printed circuit board for semiconductor memory device 有权
标题翻译：用于半导体存储器件的印刷电路板
公开(公告)号：US06781220B2
公开(公告)日：2004-08-24
申请号：US10160446
申请日：2002-05-30
申请人： Andreas Täube , Jean-Marc Dortu , Paul Schmölz , Robert Feurle
发明人： Andreas Täube , Jean-Marc Dortu , Paul Schmölz , Robert Feurle
IPC分类号： H01L23495
CPC分类号： H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/4824 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00015
摘要： In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.
摘要翻译：在半导体存储器件中，印刷电路板将存储芯片连接到外部电路。印刷电路板包括布置在列中的多个焊盘。这些焊盘将电路板连接到存储器芯片。该板还包括布置在至少两列中并通过数据连接连接到焊盘的多个数据终端。配置数据连接使得每个数据连接具有与任何其他数据连接基本相同的电气特性。

8. 发明授权

US06707705B2 Integrated dynamic memory device and method for operating an integrated dynamic memory 失效
标题翻译：用于操作集成动态存储器的集成动态存储器件和方法
公开(公告)号：US06707705B2
公开(公告)日：2004-03-16
申请号：US10113413
申请日：2002-04-01
申请人： Paul Schmölz , Jean-Marc Dortu , Robert Feurle , Andreas Täuber
发明人： Paul Schmölz , Jean-Marc Dortu , Robert Feurle , Andreas Täuber
IPC分类号： G11C1124
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076 , G11C11/4085
摘要： In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.
摘要翻译：为了操作具有存储单元阵列的集成动态存储器，该存储单元阵列具有位线和字线，用于执行存储器访问的多个单独动作 - 从一行字线的激活直到字线预充电以时钟信号的同步方式进行控制。在开始时，编写一个用于定义至少两个单独动作之间定义数量的时钟周期的值。为此，控制电路具有可编程单元。以这种方式，结合时钟电路，即使在可变时钟频率下也可以实现相对较高的数据吞吐量。

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