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1. 发明授权

US08495310B2 Method and system including plural memory controllers and a memory access control bus for accessing a memory device 有权
标题翻译：包括多个存储器控制器和用于访问存储器件的存储器访问控制总线的方法和系统
公开(公告)号：US08495310B2
公开(公告)日：2013-07-23
申请号：US12235063
申请日：2008-09-22
申请人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
发明人： Peter Gregorius , Thomas Hein , Martin Maier , Hermann Ruckerbauer , Thilo Schaffroth , Ralf Schedel , Wolfgang Spirkl , Johannes Stecker
IPC分类号： G06F13/36 , G06F13/16
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.
摘要翻译：系统和方法利用可以经由存储器件的相应端口被多个控制器或处理器核心访问的存储器件。每个控制器可以经由数据总线耦合到存储器设备的相应端口。存储器设备的每个端口可以与存储器的预定义部分相关联，从而使每个控制器访问不同部分的存储器，而不受其他控制器的干扰。公共命令/地址总线可以将多个控制器耦合到存储器设备。每个控制器可以在存储器访问控制总线上断言有效信号以获得对命令/地址总线的访问以启动存储器访问。在一些实施例中，多个存储器件可以以堆叠的存储器配置布置在存储器封装中。

2. 发明授权

US07757132B2 Memory with an output register for test data and process for testing a memory and memory module 失效
标题翻译：具有用于测试数据的输出寄存器和用于测试存储器和存储器模块的过程的存储器
公开(公告)号：US07757132B2
公开(公告)日：2010-07-13
申请号：US11752907
申请日：2007-05-23
申请人： Wolfgang Spirkl , Martin Brox
发明人： Wolfgang Spirkl , Martin Brox
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C2029/0405 , G11C2029/3602
摘要： The invention relates to a memory with a memory array with memory cells, with an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, with an output register which is connected to the input/output circuit, with the output register being used to output data via a data output, having an input register which is connected to a data input and to the input/output circuit, with the data input and the input register being used to input data into the memory cells, with test data being written to the output register in a test mode. The invention furthermore relates to a process for testing a memory and to a memory module.
摘要翻译：本发明涉及具有存储器单元的存储器阵列的存储器，其中输入/输出电路连接到存储器单元并且与存储器单元交换数据，以及连接到输入/输出电路的输出寄存器，其中输出寄存器用于经由数据输出输出数据，具有连接到数据输入端和输入/输出电路的输入寄存器，数据输入端和输入寄存器用于将数据输入存储单元测试数据以测试模式写入输出寄存器。本发明还涉及一种用于测试存储器和存储器模块的过程。

3. 发明授权

US07489153B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07489153B2
公开(公告)日：2009-02-10
申请号：US11159026
申请日：2005-06-22
申请人： Wolfgang Spirkl
发明人： Wolfgang Spirkl
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G11C29/48 , G11C29/1201
摘要： The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or data clock terminal; at least one test circuit, a respective test circuit being assigned to an input receiver and the test circuit being designed for determining at least one predetermined property of the assigned input receiver.
摘要翻译：本发明涉及可以在正常工作模式和测试模式下操作的半导体存储器件，包括：数据端子和数据时钟端子; 用于处理经由相应终端到达的信号的输入接收器，分配给数据终端和/或数据时钟端的相应输入接收器; 至少一个测试电路，相应的测试电路被分配给输入接收器，并且所述测试电路被设计用于确定所分配的输入接收器的至少一个预定属性。

4. 发明申请

US20080319693A1 Method, Device And Computer Program For Evaluating A Signal Transmission 审中-公开
标题翻译：用于评估信号传输的方法，设备和计算机程序
公开(公告)号：US20080319693A1
公开(公告)日：2008-12-25
申请号：US11764811
申请日：2007-06-19
申请人： Wolfgang Spirkl , Holger Steffens
发明人： Wolfgang Spirkl , Holger Steffens
IPC分类号： G01R25/00 , G01R29/00
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method comprises the step of obtaining a first signal of the signal from a first position of a transmission channel, and a second signal of the signal from a second position of the transmission channel, determining a delay time between the first signal and the second signal by a first degree of alikeness of the first signal and the second signal trace, and determining a direction function vector of the signal by a second degree of alikeness of the first signal and the second signal trace.
摘要翻译：一种方法包括从传输信道的第一位置获得信号的第一信号和来自传输信道的第二位置的信号的第二信号的步骤，确定第一信号和第二信号之间的延迟时间通过第一信号和第二信号迹线的第一程度的高度，并且通过第一信号和第二信号迹线的第二等级来确定信号的方向函数向量。

5. 发明申请

US20080189481A1 METHODS AND SYSTEMS FOR STORING DATA BASED ON A RELIABILITY REQUIREMENT 审中-公开
标题翻译：基于可靠性要求存储数据的方法和系统
公开(公告)号：US20080189481A1
公开(公告)日：2008-08-07
申请号：US11672427
申请日：2007-02-07
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： G06F12/00
CPC分类号： G06F12/0223 , G06F11/1008
摘要： Methods and apparatus for storing data in different regions of the memory device based on, for example, a reliability requirement of the data. A memory controller may determine a category for data, for example, high reliability data and low reliability data, prior to storing the data in memory. The data may be stored in a region of memory associated with the category of data according to a method associated with the category of data. For example, high reliability data may be stored in a particular region of memory using lower clock frequencies, with additional error correction bits, and/or at multiple redundant locations. In contrast, low reliability data may be stored other regions of the memory using higher clock frequencies, without additional error correction bits and/or at singular locations (i.e., without redundant locations.
摘要翻译：基于例如数据的可靠性要求，在存储装置的不同区域中存储数据的方法和装置。在将数据存储在存储器中之前，存储器控制器可以确定用于数据的类别，例如高可靠性数据和低可靠性数据。可以根据与数据类别相关联的方法将数据存储在与数据类别相关联的存储器的区域中。例如，高可靠性数据可以使用更低的时钟频率，附加的纠错位和/或在多个冗余位置存储在存储器的特定区域中。相比之下，低可靠性数据可以使用更高的时钟频率存储在存储器的其他区域中，而不需要额外的纠错位和/或在单个位置（即，没有冗余位置）。

6. 发明申请

US20060064620A1 Self test for the phase angle of the data read clock signal DQS 有权
标题翻译：自检相位角的数据读时钟信号DQS
公开(公告)号：US20060064620A1
公开(公告)日：2006-03-23
申请号：US11227714
申请日：2005-09-15
申请人： Justus Kuhn , Wolfgang Spirkl
发明人： Justus Kuhn , Wolfgang Spirkl
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/028 , G11C29/1201 , G11C29/50 , G11C29/50012
摘要： The invention relates to a semiconductor memory apparatus having at least one clock input contact for inputting an external clock signal, at least one clock output contact for outputting a data read clock signal for reading data stored in the semiconductor memory apparatus, at least one data contact for outputting data stored in the semiconductor memory apparatus, at least one phase adjustment device which is designed for approximately adjusting a phase of the data read clock signal on the basis of a phase of the external clock signal at least one phase difference test device which is designed for approximately detecting a phase difference between the phase of the data read clock signal and the phase of the external clock signal and for outputting a test result on the basis of the detected phase difference.
摘要翻译：本发明涉及具有用于输入外部时钟信号的至少一个时钟输入触点的半导体存储装置，至少一个时钟输出触点，用于输出用于读取存储在半导体存储装置中的数据的数据读取时钟信号，至少一个数据触点用于输出存储在所述半导体存储装置中的数据，所述至少一个相位调整装置被设计为基于所述外部时钟信号的相位近似地调整所述数据读取时钟信号的相位，所述至少一个相位差测试装置是设计用于近似地检测数据读时钟信号的相位与外部时钟信号的相位之间的相位差，并且用于基于检测到的相位差输出测试结果。

7. 发明申请

US20050030781A1 Method and arrangement for testing output circuits of high speed semiconductor memory devices 失效
标题翻译：用于测试高速半导体存储器件输出电路的方法和装置
公开(公告)号：US20050030781A1
公开(公告)日：2005-02-10
申请号：US10843383
申请日：2004-05-12
申请人： Stefan Sommer , Wolfgang Spirkl
发明人： Stefan Sommer , Wolfgang Spirkl
IPC分类号： G11C29/48 , G11C11/22
CPC分类号： G11C29/48 , G11C2029/3202
摘要： For testing or for characterizing output drivers of output circuits of high-speed semiconductor memory devices under conditions close to an application, scan elements are provided at the inputs of the output circuits. The scan elements in each case have a register function and are cascaded to form a scan chain. Via the scan chain, test data signals are applied to the inputs of the output circuits whilst bypassing a memory cell array of the semiconductor memory devices. The characterization of data signals of the high-speed semiconductor memory devices that are output by the output circuits requires only a test memory controller not connected to the data signal terminals and a passive load simulation of the application memory controller.
摘要翻译：为了在接近应用的条件下测试或表征高速半导体存储器件的输出电路的输出驱动器，在输出电路的输入处提供扫描元件。每种情况下的扫描元件都具有寄存器功能，并且级联以形成扫描链。通过扫描链，测试数据信号被施加到输出电路的输入端，同时旁路半导体存储器件的存储单元阵列。由输出电路输出的高速半导体存储器件的数据信号的表征仅需要不连接到数据信号端子的测试存储器控制器和应用存储器控制器的被动负载仿真。

8. 发明授权

US07957254B2 Concept for reducing crosstalk 有权
标题翻译：减少串扰的概念
公开(公告)号：US07957254B2
公开(公告)日：2011-06-07
申请号：US12050522
申请日：2008-03-18
申请人： Wolfgang Spirkl , Holger Steffens
发明人： Wolfgang Spirkl , Holger Steffens
IPC分类号： H04J1/12 , H04J3/10
CPC分类号： G11C7/02 , G11C11/4076 , G11C11/4096 , G11C11/4097
摘要： A device for reducing mutual crosstalk of a signal routed across a first line and a second signal routed across a second line, wherein by the mutual crosstalk at an output of the first line a first interfered signal may be obtained and at an output of the second line a second interfered signal may be obtained, comprising a modifier for modifying the first interfered signal that is interfered by crosstalk due to the second signal, and for modifying the second interfered signal that is interfered by crosstalk due to the first signal, wherein the modifier is adapted to model an interference due to the mutual crosstalk, and a combiner for combining the first interfered signal with the modified second interfered signal to obtain a first corrected signal and for combining the second interfered signal with the modified first interfered signal to obtain a second corrected signal.
摘要翻译：一种用于减少跨越第一线路路由的信号的相互串扰的设备和跨越第二线路路由的第二信号，其中通过第一线路的输出处的相互串扰可以获得第一干扰信号，并且在第二线路的输出端可以获得第二干扰信号，包括用于修改由于第二信号而被串扰干扰的第一干扰信号的修改器，以及用于修改由于第一信号而被串扰干扰的第二干扰信号，其中修饰符适于对由于相互串扰造成的干扰进行建模，以及用于将第一干扰信号与修改的第二干扰信号组合以获得第一校正信号并将第二干扰信号与修改的第一干扰信号组合以获得第二干扰信号的组合器校正信号。

9. 发明授权

US07515456B2 Memory circuit, a dynamic random access memory, a system comprising a memory and a floating point unit and a method for storing digital data 失效
标题翻译：存储器电路，动态随机存取存储器，包括存储器和浮点单元的系统以及用于存储数字数据的方法
公开(公告)号：US07515456B2
公开(公告)日：2009-04-07
申请号：US11530858
申请日：2006-09-11
申请人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
发明人： Peter Mayer , Wolfgang Spirkl , Markus Balb , Christoph Bilger , Martin Brox , Thomas Hein , Michael Richter
IPC分类号： G11C11/00
CPC分类号： G11C7/16 , G11C7/1006 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/4085 , G11C11/4096
摘要： A memory circuit comprises a D/A converter connected with an input/output circuit and with a writing circuit, wherein the D/A converter converts a digital data with at least two digital bits received from the input/output circuit to one analog value and forwards the analog value to the writing circuit, wherein the digital data is at least a part of a floating point number, wherein the writing circuit writes the analog value in at least one selected memory cell, and an A/D converter connected with a reading circuit and with the input/output circuit, wherein the reading circuit reads an analog value from a selected memory cell and forwards the analog value to the A/D converter, wherein the A/D converter converts the analog value to digital data, and wherein the A/D converter forwards the digital data to the input/output circuit. Furthermore, a method is provided for reading data from at least one memory cell of a memory, wherein an analog value is read from the memory cell and the analog value is corrected according to a correction factor representing a storage time the analog value was stored and wherein the corrected analog value is converted to digital data.
摘要翻译：存储电路包括与输入/输出电路和写入电路连接的D / A转换器，其中D / A转换器将具有从输入/输出电路接收的至少两个数字位的数字数据转换成一个模拟值，将模拟值转发到写入电路，其中数字数据是浮点数的至少一部分，其中写入电路将模拟值写入至少一个选择的存储单元，以及与读取器连接的A / D转换器电路和输入/输出电路，其中读取电路从所选择的存储器单元读取模拟值并将模拟值转发到A / D转换器，其中A / D转换器将模拟值转换为数字数据，其中 A / D转换器将数字数据转发到输入/输出电路。此外，提供一种用于从存储器的至少一个存储单元读取数据的方法，其中从存储器单元读取模拟值，并且根据表示存储模拟值的存储时间的校正因子来校正模拟值，以及其中所述经修正的模拟值被转换为数字数据。

10. 发明申请

US20090045856A1 CLOCK SIGNAL SYNCHRONIZING DEVICE WITH INHERENT DUTY-CYCLE CORRECTION CAPABILITY 失效
标题翻译：具有足够的周期校正能力的时钟信号同步器件
公开(公告)号：US20090045856A1
公开(公告)日：2009-02-19
申请号：US11838634
申请日：2007-08-14
申请人： Wolfgang Spirkl , Martin Brox , Holger Steffens
发明人： Wolfgang Spirkl , Martin Brox , Holger Steffens
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.
摘要翻译：一个方面涉及一种时钟信号同步装置，特别涉及具有校正静态占空比偏移和滤波时钟抖动能力的延迟锁定环（DLL）。一个方面涉及具有校正静态占空比偏移和滤波时钟抖动能力的时钟信号同步方法。根据一个方面，提供了一种时钟信号同步装置，其包括具有可变延迟时间并延迟输入时钟信号或由其产生的信号的延迟电路以输出延迟的时钟信号。还包括用于反相延迟时钟信号以输出反相延迟时钟信号的否定器。还包括延迟控制电路，用于控制延迟电路以调整输入时钟信号和反相延迟时钟信号之间的相位关系以及相位插值器。当输入时钟信号和反相延迟时钟信号基本上同相时，相位内插器被激活，并将输入时钟信号乘以基本上为（1-p）的因子到反相延迟的时钟信号乘以基本上为p的因子将复合信号输出到延迟电路，p是大于或等于0且小于或等于1的实数。

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