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1. 发明授权

US07064067B1 Reduction of lateral silicide growth in integrated circuit technology 有权
标题翻译：降低集成电路技术中的侧硅化物生长
公开(公告)号：US07064067B1
公开(公告)日：2006-06-20
申请号：US10770905
申请日：2004-02-02
申请人： Paul L. King , Simon Siu-Sing Chan , Jeffrey P. Patton , Minh Van Ngo
发明人： Paul L. King , Simon Siu-Sing Chan , Jeffrey P. Patton , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物。在半导体衬底中形成源极/漏极结。在源极/漏极区域和栅极上形成中间相硅化物。去除侧壁间隔物。由中间相硅化物形成最终相硅化物。在半导体衬底上沉积层间电介质，然后在层间电介质中形成接触到最终相硅化物。

2. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

3. 发明授权

US07670915B1 Contact liner in integrated circuit technology 有权
标题翻译：接触式衬板集成电路技术
公开(公告)号：US07670915B1
公开(公告)日：2010-03-02
申请号：US10791096
申请日：2004-03-01
申请人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
发明人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
IPC分类号： H01L21/20
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结和栅极上形成硅化物。在半导体衬底的上方形成有具有接触孔的层间电介质。接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。

4. 发明授权

US08102009B2 Integrated circuit eliminating source/drain junction spiking 有权
标题翻译：集成电路消除源极/漏极结尖峰
公开(公告)号：US08102009B2
公开(公告)日：2012-01-24
申请号：US11538156
申请日：2006-10-03
申请人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
发明人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
IPC分类号： H01L29/76
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.
摘要翻译：提供了具有半导体衬底的集成电路。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。金属层在半导体衬底上，金属层与半导体衬底反应形成硅化物的早期阶段。在硅化物的正下方，注入浅的源极/漏极结。形成硅化物的最终相。层间电介质在半导体衬底上方，并且与硅化物形成接触。

5. 发明授权

US06969678B1 Multi-silicide in integrated circuit technology 失效
标题翻译：集成电路技术中的多硅化物
公开(公告)号：US06969678B1
公开(公告)日：2005-11-29
申请号：US10700711
申请日：2003-11-03
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供一种形成集成电路的方法和集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

6. 发明授权

US07843015B2 Multi-silicide system in integrated circuit technology 有权
标题翻译：集成电路技术中的多硅化物系统
公开(公告)号：US07843015B2
公开(公告)日：2010-11-30
申请号：US11229188
申请日：2005-09-15
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/02
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译：提供集成电路。在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。底部和顶部硅化物金属形成其硅化物。介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

7. 发明授权

US07132352B1 Method of eliminating source/drain junction spiking, and device produced thereby 有权
标题翻译：消除源极/漏极结尖峰的方法，以及由此产生的器件
公开(公告)号：US07132352B1
公开(公告)日：2006-11-07
申请号：US10913184
申请日：2004-08-06
申请人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
发明人： Simon Siu-Sing Chan , Paul R. Besser , Jeffrey P. Patton
IPC分类号： H01L21/28
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底上形成金属层，金属层与半导体衬底反应形成硅化物的早期阶段。在硅化物的正下方形成植入的浅源极/漏极结。形成硅化物的最终相。在半导体衬底上沉积层间电介质，然后与硅化物形成接触。

8. 发明授权

US07023059B1 Trenches to reduce lateral silicide growth in integrated circuit technology 有权
标题翻译：沟槽减少集成电路技术中的侧向硅化物生长
公开(公告)号：US07023059B1
公开(公告)日：2006-04-04
申请号：US10791094
申请日：2004-03-01
申请人： Darin A. Chan , Simon Siu-Sing Chan , Jeffrey P. Patton , Jacques J. Bertrand
发明人： Darin A. Chan , Simon Siu-Sing Chan , Jeffrey P. Patton , Jacques J. Bertrand
IPC分类号： H01L29/94
CPC分类号： H01L29/66636 , H01L21/76897 , H01L29/665 , H01L29/6653
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极区域和栅极上形成硅化物。在栅极周围的半导体衬底中形成沟槽。在半导体衬底上沉积层间电介质，然后与硅化物形成接触。

9. 发明授权

US07250667B2 Selectable open circuit and anti-fuse element 有权
标题翻译：可选开路和反熔丝元件
公开(公告)号：US07250667B2
公开(公告)日：2007-07-31
申请号：US11306663
申请日：2006-01-05
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L29/00
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。源极/漏极结在半导体衬底中。硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。层间电介质在半导体衬底之上。触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

10. 发明授权

US07015076B1 Selectable open circuit and anti-fuse element, and fabrication method therefor 失效
标题翻译：可选开路和反熔丝元件及其制造方法
公开(公告)号：US07015076B1
公开(公告)日：2006-03-21
申请号：US10791098
申请日：2004-03-01
申请人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
发明人： Darin A. Chan , Simon Siu-Sing Chan , Paul L. King
IPC分类号： H01L21/82
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.
摘要翻译：提供了一种形成集成电路的方法，该半导体衬底在半导体衬底反应形成这种硅化物时，掺杂有一定类型的可氧化掺杂剂的分解与硅化物顶表面的浓度。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。在源极/漏极结上形成硅化物，掺杂剂分离到硅化物的顶表面。分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。在半导体衬底上沉积层间电介质。接触点和连接点然后在层间电介质中形成到硅化物之上的氧化掺杂剂的绝缘层。

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