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1. 发明授权

US06686617B2 Semiconductor chip having both compact memory and high performance logic 有权
标题翻译：具有紧凑型存储器和高性能逻辑的半导体芯片
公开(公告)号：US06686617B2
公开(公告)日：2004-02-03
申请号：US09878804
申请日：2001-06-11
申请人： Paul D. Agnello , Bomy A. Chen , Scott W. Crowder , Ramachandra Divakaruni , Subramanian S. Iyer , Dennis Sinitsky
发明人： Paul D. Agnello , Bomy A. Chen , Scott W. Crowder , Ramachandra Divakaruni , Subramanian S. Iyer , Dennis Sinitsky
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/823443 , H01L21/82345 , H01L27/10873 , H01L27/10894
摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.
摘要翻译：在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件逻辑区域。将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。还公开了由该方法的各种实施方案产生的芯片结构。

2. 发明授权

US06287913B1 Double polysilicon process for providing single chip high performance logic and compact embedded memory structure 有权
标题翻译：双晶硅工艺，提供单芯片高性能逻辑和紧凑型嵌入式存储器结构
公开(公告)号：US06287913B1
公开(公告)日：2001-09-11
申请号：US09427506
申请日：1999-10-26
申请人： Paul D. Agnello , Bomy A. Chen , Scott W. Crowder , Ramachandra Divakaruni , Subramanian S. Iyer , Dennis Sinitsky
发明人： Paul D. Agnello , Bomy A. Chen , Scott W. Crowder , Ramachandra Divakaruni , Subramanian S. Iyer , Dennis Sinitsky
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L21/823443 , H01L21/82345 , H01L27/10873 , H01L27/10894
摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.
摘要翻译：在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件逻辑区域。将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。还公开了由该方法的各种实施方案产生的芯片结构。

3. 发明授权

US06429101B1 Method of forming thermally stable polycrystal to single crystal electrical contact structure 失效
标题翻译：将热稳定多晶体形成为单晶电接触结构的方法
公开(公告)号：US06429101B1
公开(公告)日：2002-08-06
申请号：US09240753
申请日：1999-01-29
申请人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
发明人： Ricky S. Amos , Arne W. Ballantine , Gregory Bazan , Bomy A. Chen , Douglas D. Coolbaugh , Ramachandra Divakaruni , Heidi L. Greer , Herbert L. Ho , Joseph F. Kudlacik , Bernard P. Leroy , Paul C. Parries , Gary L. Patton
IPC分类号： H01L2120
CPC分类号： H01L21/02126 , H01L21/0214 , H01L21/02236 , H01L21/02249 , H01L21/02255 , H01L21/31662
摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.
摘要翻译：一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

4. 发明授权

US5556802A Method of making corrugated vertical stack capacitor (CVSTC) 失效
标题翻译：波纹垂直叠层电容器（CVSTC）制作方法
公开(公告)号：US5556802A
公开(公告)日：1996-09-17
申请号：US486630
申请日：1995-06-07
申请人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
发明人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/949
摘要： A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact. Depositing a first silicon material over selected mandrels, the top layer, and the contact intermediate the selected mandrels. Depositing photoresist over the first silicon. Etching the photoresist and the first silicon to the mandrel height to establish a node capacitor electrode. Stripping the photoresist remaining. Stripping the first oxide. Depositing a second oxide over the node electrode to establish a capacitor dielectric layer. Depositing a second silicon material over the dielectric layer to establish a plate capacitor electrode.
摘要翻译：一种在具有在顶层之下具有接触的基底上形成电容器的方法，包括以下步骤：在光致抗蚀剂材料层上旋转。将光致抗蚀剂曝光以建立驻波图案以固定由分离区域分离的光致抗蚀剂的突出部分。每个突出部分从顶层延伸到顶部。显影光致抗蚀剂以在每个突起处固定一个正面，每个面从顶层延伸到顶部。沉积第一氧化物中间体以使第一氧化物积累至至少等于突出高度的氧化物高度。蚀刻第一氧化物以暴露每个顶部。溶解光致抗蚀剂以露出氧化物心轴。每个心轴将心轴高度从顶层延伸到心轴顶部; 每个心轴具有在顶层和心轴顶部之间的中心轴。蚀刻顶层以暴露接触。将第一硅材料沉积在选定的心轴，顶层和选定的心轴之间的接触之上。在第一硅上沉积光致抗蚀剂。将光致抗蚀剂和第一硅蚀刻到心轴高度以建立节点电容器电极。剥离残留的光致抗蚀剂。剥去第一氧化物。在节点电极上沉积第二氧化物以建立电容器介电层。在电介质层上沉积第二硅材料以建立平板电容器电极。

5. 发明授权

US06518614B1 Embedded one-time programmable non-volatile memory using prompt shift device 有权
标题翻译：嵌入式一次性可编程非易失性存储器，使用快速移位装置
公开(公告)号：US06518614B1
公开(公告)日：2003-02-11
申请号：US09683809
申请日：2002-02-19
申请人： Matthew J. Breitwisch , Bomy A. Chen , Chung H. Lam
发明人： Matthew J. Breitwisch , Bomy A. Chen , Chung H. Lam
IPC分类号： H01L27108
CPC分类号： H01L27/11206 , H01L27/112
摘要： The present invention provides a programmable element that can be programmed using relatively low-voltages (less than about 5 V) for use in one time programmable non-volatile memory storage or other high-density application. The low-voltage programmable element is a field effect transistor (FET) device that includes source and drain elements, which are separated by a channel region, and a gate region, present atop a portion of the channel region. The source and drain elements are not located beneath the gate region and the FET includes no extension implant regions present therein.
摘要翻译：本发明提供一种可编程元件，其可以使用相对较低的电压（小于约5V）进行编程，以用于一次性可编程非易失性存储器存储或其它高密度应用。低电压可编程元件是场效应晶体管（FET）器件，其包括由沟道区分隔开的源极和漏极元件以及存在于沟道区域的一部分顶部的栅极区域。源极和漏极元件不位于栅极区域下方，并且FET不包括存在于其中的延伸注入区域。

6. 发明授权

US06429091B1 Patterned buried insulator 失效
标题翻译：图案埋地绝缘子
公开(公告)号：US06429091B1
公开(公告)日：2002-08-06
申请号：US09733324
申请日：2000-12-08
申请人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
发明人： Bomy A. Chen , Alexander Hirsch , Sundar K. Iyer , Nivo Rovedo , Hsing-Jen Wann , Ying Zhang
IPC分类号： H01L2176
CPC分类号： H01L29/0653 , H01L21/7621 , H01L21/76224 , H01L21/7624 , H01L21/823418 , H01L21/823481
摘要： A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.
摘要翻译：在源极和漏极之下形成图案化的掩埋绝缘体，通过在身体区域上形成掩模并在要形成源极和漏极的区域中注入一定量的n或p型离子，然后蚀刻STI并蚀刻出植入区。光氧化之后是STI中的共形氧化物沉积以及蚀刻区域，从而仅在需要时形成掩埋氧化物。

7. 发明授权

US07329602B2 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US07329602B2
公开(公告)日：2008-02-12
申请号：US11203944
申请日：2005-08-15
申请人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
发明人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

8. 发明授权

US06294449B1 Self-aligned contact for closely spaced transistors 失效
标题翻译：紧密间隔晶体管的自对准触点
公开(公告)号：US06294449B1
公开(公告)日：2001-09-25
申请号：US09447627
申请日：1999-11-23
申请人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
发明人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.
摘要翻译：一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

9. 发明授权

US06238963B1 Damascene process for forming ferroelectric capacitors 失效
标题翻译：用于形成铁电电容器的镶嵌工艺
公开(公告)号：US06238963B1
公开(公告)日：2001-05-29
申请号：US09447631
申请日：1999-11-23
申请人： Bomy A. Chen , Chorng-Lii Hwang
发明人： Bomy A. Chen , Chorng-Lii Hwang
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/3212 , H01L27/10852 , H01L28/55
摘要： The difficulty of etching noble metals in ferroelectric capacitors is eliminated by a damascene process that employs chemical-mechanical polishing to remove the unwanted material, resulting in a lower electrode formed in an aperture in a dielectric, having a flat central portion and a wall extending from the central portion to the top surface of the surrounding dielectric; and an upper electrode formed in a two-level aperture, so that the upper electrode structure has a flat central portion, a first vertical wall extending from the central portion to a rim surrounding the central portion and extending over the wall of the lower electrode, and a second vertical wall extending from the rim to the top surface of a surrounding dielectric.
摘要翻译：通过使用化学机械抛光去除不想要的材料的镶嵌工艺来消除在铁电电容器中蚀刻贵金属的难度，导致形成在电介质的孔中的下电极，具有平坦的中心部分和从围绕电介质顶表面的中心部分; 以及形成在两级孔中的上电极，使得上电极结构具有平坦的中心部分，从中心部分延伸到围绕中心部分并在下电极的壁上延伸的边缘的第一垂直壁，以及从边缘延伸到周围电介质的顶表面的第二垂直壁。

10. 发明授权

US07438822B2 Apparatus and method for shielding a wafer from charged particles during plasma etching 失效
标题翻译：在等离子体蚀刻期间屏蔽晶片与带电粒子的装置和方法
公开(公告)号：US07438822B2
公开(公告)日：2008-10-21
申请号：US11260375
申请日：2005-10-28
申请人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
发明人： Hongwen Yan , Brian L. Ji , Siddhartha Panda , Richard Wise , Bomy A. Chen
IPC分类号： C23F1/00
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.
摘要翻译：一种等离子体蚀刻系统，其具有带有磁体的晶片卡盘，该磁体在晶片上施加磁场以将晶片免受带电粒子的影响。磁场与晶片平行，并且在晶片表面附近最强。磁场可以是直的或圆形的。在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，离子被静电排斥偏转。允许中性物质通过磁场，并且它们与晶片碰撞。中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。此外，由于调味过程通常依赖于带电粒子的蚀刻，所以磁场可以保护晶片免受调节过程的调节过程，以便从室表面清洁不需要的膜。

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