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1. 发明申请

US20130159664A1 Infrastructure Support for Accelerated Processing Device Memory Paging Without Operating System Integration 有权
标题翻译：基础设施支持加速处理设备内存寻呼，无需操作系统集成
公开(公告)号：US20130159664A1
公开(公告)日：2013-06-20
申请号：US13325282
申请日：2011-12-14
申请人： Paul BLINZER , Leendert Peter Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Roy Woller , Arshad Rahman
发明人： Paul BLINZER , Leendert Peter Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Roy Woller , Arshad Rahman
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F12/1081 , G06F2009/3883 , G06F2212/683
摘要： In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.
摘要翻译：在组合的CPU / APD架构系统的CPU中，CPU具有多个CPU内核，每个核具有用于接收物理页表/页目录基地址的第一机器特定寄存器，用于接收物理地址指向到由通信地耦合到APD的IOMMUv2控制的位置，以及当被执行时导致向包含在第二机器特定寄存器中的物理地址发出写入通知的微代码; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中，物理地址能够接收影响IOMMUv2页表无效的写入。

2. 发明授权

US08578129B2 Infrastructure support for accelerated processing device memory paging without operating system integration 有权
标题翻译：基础架构支持加速处理设备内存分页，无需操作系统集成
公开(公告)号：US08578129B2
公开(公告)日：2013-11-05
申请号：US13325282
申请日：2011-12-14
申请人： Paul Blinzer , Leendert Peter Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Roy Woller , Arshad Rahman
发明人： Paul Blinzer , Leendert Peter Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Roy Woller , Arshad Rahman
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F9/3004 , G06F9/3881 , G06F12/1081 , G06F2009/3883 , G06F2212/683
摘要： In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.
摘要翻译：在CPU中，具有多个CPU核心的CPU，每个核心具有第一机器特定寄存器，第二机器特定寄存器和微代码，当被执行时，将对包含在第二机器特定寄存器中的物理地址发出写入通知; 在CPU核心的第一机器特定寄存器中接收物理页表/页目录基地址，在CPU核心的第二机器特定寄存器中接收指向由IOMMUv2控制的位置的物理地址，确定控制已经更新了CPU核心的寄存器，并且响应于控制寄存器被更新的确定，执行CPU核心中的微代码，使得向第二机器特定寄存器中包含的物理地址发出写入通知，其中，物理地址能够接收影响IOMMUv2页表无效的写入。

3. 发明授权

US08797332B2 Device discovery and topology reporting in a combined CPU/GPU architecture system 有权
标题翻译：组合CPU / GPU架构系统中的设备发现和拓扑报告
公开(公告)号：US08797332B2
公开(公告)日：2014-08-05
申请号：US13325824
申请日：2011-12-14
申请人： Paul Blinzer , Leendert Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Woller , Arshad Rahman
发明人： Paul Blinzer , Leendert Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Woller , Arshad Rahman
IPC分类号： G06F15/00 , G06T1/00 , G06F15/16 , G06T1/60
CPC分类号： G06T1/20 , G06F9/30003
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性系统。组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

4. 发明申请

US20120162234A1 Device Discovery and Topology Reporting in a Combined CPU/GPU Architecture System 有权
标题翻译：组合CPU / GPU架构系统中的设备发现和拓扑报告
公开(公告)号：US20120162234A1
公开(公告)日：2012-06-28
申请号：US13325824
申请日：2011-12-14
申请人： Paul Blinzer , Leendert Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Woller , Arshad Rahman
发明人： Paul Blinzer , Leendert Van Doorn , Gongxian Jeffrey Cheng , Elene Terry , Thomas Woller , Arshad Rahman
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06F9/30003
摘要： Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.
摘要翻译：提供了作为组合的CPU / APD架构系统的一个方面的方法和装置，用于发现和报告与有效地调度和分发计算任务到组合的CPU / APD架构的各种计算资源相关的设备和系统拓扑的属性系统。组合的CPU / APD架构将CPU和APD统一在灵活的计算环境中。在一些实施例中，组合的CPU / APD架构能力在单个集成电路中实现，其单元可以包括一个或多个CPU核心和一个或多个APD核心。组合的CPU / APD架构创建了可以构建现有和新的编程框架，语言和工具的基础。

5. 发明授权

US08489752B2 Method and system for controlling bus access 有权
标题翻译：控制总线访问的方法和系统
公开(公告)号：US08489752B2
公开(公告)日：2013-07-16
申请号：US12475134
申请日：2009-05-29
申请人： Warren Kruger , Zohair Hyder , Elene Terry , Xidong Wang
发明人： Warren Kruger , Zohair Hyder , Elene Terry , Xidong Wang
IPC分类号： G06F15/16
CPC分类号： G06F13/387
摘要： A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.
摘要翻译：一种用于控制多个客户端与中央组件之间的通信的系统和方法。本发明的实施例包括连接客户机和中央组件的一个或多个总线。该实施例还包括控制模块，其被配置为从客户端接收ASK消息并向客户端发出GO命令。每个ASK消息表示来自客户端访问中央组件的请求。到客户端的每个GO命令都代表该客户端访问中央组件的权限。控制模块包括延迟GO命令的延迟级。延迟可能会因客户端而异。选择延迟阶段的数量使得对于所有的客户端，发出GO命令与来自客户端的通信中心组件的接收之间的延迟是相同的。

6. 发明申请

US20090313323A1 Method and System for Controlling Bus Access 有权
标题翻译：控制总线访问的方法和系统
公开(公告)号：US20090313323A1
公开(公告)日：2009-12-17
申请号：US12475134
申请日：2009-05-29
申请人： Warren Kruger , Zohair Hyder , Elene Terry , Xidong Wang
发明人： Warren Kruger , Zohair Hyder , Elene Terry , Xidong Wang
IPC分类号： G06F15/16
CPC分类号： G06F13/387
摘要： A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.
摘要翻译：一种用于控制多个客户端与中央组件之间的通信的系统和方法。本发明的实施例包括连接客户机和中央组件的一个或多个总线。该实施例还包括控制模块，其被配置为从客户端接收ASK消息并向客户端发出GO命令。每个ASK消息表示来自客户端访问中央组件的请求。到客户端的每个GO命令都代表该客户端访问中央组件的权限。控制模块包括延迟GO命令的延迟级。延迟可能会因客户端而异。选择延迟阶段的数量使得对于所有的客户端，发出GO命令与来自客户端的通信中心组件的接收之间的延迟是相同的。

7. 发明申请

US20160316110A1 LOW-LATENCY TIMING CONTROL 有权
标题翻译：低估时序控制
公开(公告)号：US20160316110A1
公开(公告)日：2016-10-27
申请号：US14694764
申请日：2015-04-23
申请人： Jonathan Ross , Robert Allen Shearer , Elene Terry
发明人： Jonathan Ross , Robert Allen Shearer , Elene Terry
IPC分类号： H04N5/073 , H04N5/06 , H04N5/235 , H04L7/10
CPC分类号： H04N5/0733 , H04L7/10 , H04N5/06 , H04N5/2258 , H04N5/232 , H04N5/2353
摘要： A timing control system includes one or more device processors operatively coupled to one or more devices, a counter connected to the device processor(s), and a plurality of timing registers operatively coupled to the counter, each of the timing registers configured to store a value indicating a time at which an event is to be initiated at a corresponding one of the device(s). The system also includes a pulse generator operatively coupled to the counter and the timing registers, the pulse generator configured to generate one or more associated general-purpose input/output (GPIO) output signals, and send to each of the one or more devices an associated GPIO output signal to initiate the event at a plurality of the one or more devices in coordination with one another or to initiate the event at one of the one or more devices in coordination with another event at that device.
摘要翻译：定时控制系统包括可操作地耦合到一个或多个设备的一个或多个设备处理器，连接到设备处理器的计数器以及可操作地耦合到计数器的多个定时寄存器，每个定时寄存器被配置为存储指示在相应的一个设备上发起事件的时间的值。该系统还包括可操作地耦合到计数器和定时寄存器的脉冲发生器，该脉冲发生器经配置以产生一个或多个相关联的通用输入/输出（GPIO）输出信号，并且向一个或多个设备中的每一个发送相关联的GPIO输出信号，以在多个一个或多个设备彼此协调地发起事件，或者与该设备上的另一个事件协调地在一个或多个设备之一发起事件。

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