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1. 发明授权

US06754776B2 Method and system for logical partitioning of cache memory structures in a partitoned computer system 失效
标题翻译：分区计算机系统中高速缓存存储器结构的逻辑分区方法和系统
公开(公告)号：US06754776B2
公开(公告)日：2004-06-22
申请号：US09861258
申请日：2001-05-17
申请人： Patrick N. Conway , Kazunori Masuyama , Takeshi Shimizu , Toshio Ogawa , Martin Sodos , Sudheer Miryala , Jeremy Farrell
发明人： Patrick N. Conway , Kazunori Masuyama , Takeshi Shimizu , Toshio Ogawa , Martin Sodos , Sudheer Miryala , Jeremy Farrell
IPC分类号： G06F1200
CPC分类号： G06F12/084 , G06F12/0813
摘要： A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.
摘要翻译：公开了在计算机域之间逻辑分区共享存储器结构的系统和方法。在一个实施例中，为每个域分配唯一的地址空间标识符。唯一地址空间标识符优选地具有标签扩展和索引扩展位。这允许使用标签扩展和索引扩展位来扩展常规本地域地址的标签和索引位。可以使用扩展索引值来访问共享存储器结构中的数据条目。命中可以使用扩展标签值来确定。

2. 发明授权

US06961761B2 System and method for partitioning a computer system into domains 有权
标题翻译：将计算机系统划分为域的系统和方法
公开(公告)号：US06961761B2
公开(公告)日：2005-11-01
申请号：US09861293
申请日：2001-05-17
申请人： Kazunori Masuyama , Patrick N. Conway , Hitoshi Oi , Jeremy Farrell , Sudheer Miryala , Yukio Nishimura , Prabhu Murthy
发明人： Kazunori Masuyama , Patrick N. Conway , Hitoshi Oi , Jeremy Farrell , Sudheer Miryala , Yukio Nishimura , Prabhu Murthy
IPC分类号： G06F15/177 , G06F9/50 , H04L12/24
CPC分类号： H04L41/082 , H04L41/0803 , H04L41/12
摘要： A domain partitioning system for a multi-node computer system is disclosed. An external server manager is coupled to a domain configuration unit by a dedicated sideband channel. The server manager has write privileges to the domain configuration unit that allows the server manager to control the domain partitioning and the routing tables. None of the domains of the computer system are permitted write access to the domain configuration unit. In one embodiment, the domain configuration unit is a set of domain partition registers and routing table registers coupled to a system interconnect.
摘要翻译：公开了一种用于多节点计算机系统的域分割系统。外部服务器管理器通过专用边带信道耦合到域配置单元。服务器管理员对域配置单元具有写入权限，允许服务器管理器控制域分区和路由表。计算机系统的任何域都不允许对域配置单元进行写访问。在一个实施例中，域配置单元是耦合到系统互连的一组域分区寄存器和路由表寄存器。

3. 发明授权

US07380001B2 Fault containment and error handling in a partitioned system with shared resources 有权
标题翻译：具有共享资源的分区系统中的故障控制和错误处理
公开(公告)号：US07380001B2
公开(公告)日：2008-05-27
申请号：US10150618
申请日：2002-05-17
申请人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
发明人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
IPC分类号： G06F15/173 , G06F15/00 , G06F11/00
CPC分类号： H04L41/12 , H04L41/0654 , H04L43/0817
摘要： A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.
摘要翻译：在分区计算机系统中的域内的用于故障容纳和错误处理的系统和方法包括具有对资源定义表的读取和写入访问的系统管理器。系统管理器适用于在域内发生故障时停止系统，识别与故障域相关联的分配资源，识别非故障域，并退出非故障域的静默模式，从而在失败的域。系统管理员通过取消分配给故障域的资源来进一步处理故障域内的错误，以使资源变得可用于非故障域。

4. 发明授权

US07194517B2 System and method for low overhead message passing between domains in a partitioned server 失效
标题翻译：分区服务器中域之间低开销消息传递的系统和方法
公开(公告)号：US07194517B2
公开(公告)日：2007-03-20
申请号：US10154100
申请日：2002-05-21
申请人： Patrick N. Conway , Jeremy J. Farrell , Kazunori Masuyama , Takeshi Shimizu , Sudheer Miryala
发明人： Patrick N. Conway , Jeremy J. Farrell , Kazunori Masuyama , Takeshi Shimizu , Sudheer Miryala
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： H04L67/2852 , H04L69/329
摘要： A system and method for passing messages between domains with low overhead in a multi-node computer system. A CPU node in a sending domain issues a request to a memory node in a receiving domain using memory-mapped input/output window. This causes the message to be transmitted to a coherent space of the receiving domain. All messages are cache-line in size. A small portion of each cache line, cyclic counter field, is overwritten before the cache line is written in the coherent address space of the receiving domain. A massaging driver polls the cyclic count field of the cache line in the processor cache to determine when the next message is written in the coherent address space of the receiving domain. This allows the CPU to detect when the last received message is written into the coherent address space of the receiving domain without generating transactions on CPU interface.
摘要翻译：一种用于在多节点计算机系统中具有低开销的域之间传递消息的系统和方法。发送域中的CPU节点使用存储器映射的输入/输出窗口向接收域中的存储器节点发出请求。这导致消息被发送到接收域的相干空间。所有消息都是高速缓存行大小。在将高速缓存行写入接收域的相干地址空间之前，每个高速缓存行的循环计数器字段的一小部分被重写。按摩驱动程序轮询处理器高速缓存中的高速缓存行的循环计数字段，以确定下一个消息何时被写入接收域的相干地址空间。这允许CPU检测最后接收的消息何时被写入接收域的相干地址空间，而不在CPU接口上生成事务。

5. 发明授权

US07315895B2 Fault containment and error handling in a partitioned system with shared resources 有权
公开(公告)号：US07315895B2
公开(公告)日：2008-01-01
申请号：US10150618
申请日：2002-05-17
申请人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
发明人： Kazunori Masuyama , Yasushi Umezawa , Jeremy J. Farrell , Sudheer Miryala , Takeshi Shimizu , Hitoshi Oi , Patrick N. Conway
IPC分类号： G06F15/173 , G06F15/00 , G06F11/00
摘要： A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occurs within a domain, identify an allocated resource associated with the failed domain, identify a non-failed domain, and exit the quiesce mode for the non-failed domain, thereby containing a failure within the failed domain. The system manager further handles an error within the failed domain by deallocating a resource allocated to the failed domain so that the resource becomes available to non-failed domains.

6. 发明授权

US07159017B2 Routing mechanism for static load balancing in a partitioned computer system with a fully connected network 有权
标题翻译：具有完全连接网络的分区计算机系统中的静态负载平衡的路由机制
公开(公告)号：US07159017B2
公开(公告)日：2007-01-02
申请号：US10077144
申请日：2002-02-15
申请人： Hitoshi Oi , Patrick N. Conway , Takeshi Shimizu , Kazunori Masuyama , Sudheer Miryala , Jeremy J. Farrell , Norio Kaido
发明人： Hitoshi Oi , Patrick N. Conway , Takeshi Shimizu , Kazunori Masuyama , Sudheer Miryala , Jeremy J. Farrell , Norio Kaido
IPC分类号： G06F15/177
CPC分类号： H04L47/125 , H04L45/04
摘要： A mechanism for balancing message traffic in a multi-chassis fully interconnected computer system partitioned into multiple domains allows the system to identify I/O transactions, to route I/O transactions over inter-domain cables, and to route non-I/O transactions over intra-domain cables. This beneficially reduces message traffic congestion on intra-domain cables.
摘要翻译：用于平衡分为多个域的多机箱完全互连的计算机系统中的消息流量的机制允许系统识别I / O事务，通过域间电缆路由I / O事务以及路由非I / O事务通过域内电缆。有益地减少域内线缆的消息流量拥塞。

7. 发明授权

US06742101B2 Scalable and flexible method for address space decoding in a multiple node computer system 有权
标题翻译：用于多节点计算机系统中的地址空间解码的可扩展且灵活的方法
公开(公告)号：US06742101B2
公开(公告)日：2004-05-25
申请号：US10153480
申请日：2002-05-21
申请人： Sudheer Miryala , Jeremy J. Farrell , Kazunori Masuyama , Patrick N. Conway
发明人： Sudheer Miryala , Jeremy J. Farrell , Kazunori Masuyama , Patrick N. Conway
IPC分类号： G06F1210
CPC分类号： G06F15/17375
摘要： A multi-node computer system includes a plurality of I/O nodes, CPU nodes, memory nodes, and hybrid nodes connected via an interconnect. A CPU node or an I/O node issues a request. An address decoder residing in the interconnect decodes the request to determine whether the request is a coherent memory request. The address decoder also determines a physical destination node address of the request based on a logical node address stored in the request.
摘要翻译：多节点计算机系统包括通过互连连接的多个I / O节点，CPU节点，存储器节点和混合节点。 CPU节点或I / O节点发出请求。驻留在互连中的地址解码器解码请求以确定请求是否是相干存储器请求。地址解码器还基于存储在请求中的逻辑节点地址来确定请求的物理目的地节点地址。

8. 发明授权

US07213081B2 Dynamic determination of memory mapped input output range granularity for multi-node computer system 失效
标题翻译：动态确定多节点计算机系统的内存映射输入输出范围粒度
公开(公告)号：US07213081B2
公开(公告)日：2007-05-01
申请号：US10122043
申请日：2002-04-11
申请人： Prabhunandan B. Narasimhamurthy , Yukio Nishimura , Sudheer Miryala , Kazunori Masuyama
发明人： Prabhunandan B. Narasimhamurthy , Yukio Nishimura , Sudheer Miryala , Kazunori Masuyama
IPC分类号： G06F3/00
CPC分类号： G06F12/063
摘要： A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.
摘要翻译：一种方法和系统支持多节点计算机系统中的存储器映射设备的动态支持。中央处理单元（CPU）节点之一确定所有MMIO设备所需的MMIO地址空间的总量，并生成优化的粒度以支持MMIO地址空间的总量。基于粒度，CPU节点控制器配置IO节点和CPU节点控制器中的互连和其他MMIO寄存器的MMIO范围寄存器，以支持系统的MMIO地址空间要求的动态更改。

9. 发明授权

US07076576B2 Data transfer in multi-node computer system 失效
公开(公告)号：US07076576B2
公开(公告)日：2006-07-11
申请号：US10114525
申请日：2002-04-01
申请人： Yukio Nishimura , Prabhunandan B. Narasimharmurthy , Sudheer Miryala , Kazunori Masuyama
发明人： Yukio Nishimura , Prabhunandan B. Narasimharmurthy , Sudheer Miryala , Kazunori Masuyama
IPC分类号： G06F13/00
CPC分类号： G06F15/17375
摘要： A method and system transfers data between intra-node firmware and inter-nodes firmware in a multi-node computer system using reduced hardware resources. A set of control codes and data transfer functions are provided to enable data communications between computer nodes and inter-nodes controller through a one-byte control module and a one-byte data module.

10. 发明授权

US06862634B2 Mechanism to improve performance in a multi-node computer system 有权
标题翻译：提高多节点计算机系统性能的机制
公开(公告)号：US06862634B2
公开(公告)日：2005-03-01
申请号：US10150276
申请日：2002-05-17
申请人： Jeremy J. Farrell , Kazunori Masuyama , Sudheer Miryala , Patrick Conway
发明人： Jeremy J. Farrell , Kazunori Masuyama , Sudheer Miryala , Patrick Conway
IPC分类号： G06F15/167 , H04L12/56 , H04L29/06 , G06F3/00
CPC分类号： H04L69/12
摘要： In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to a network interface controller (NIC) for transferring data packets on a network. Each NIC is memory-mapped. Part of the system address space forms a send window for each NIC connected to a corresponding switch. A mechanism for controlling data packets transmission is defined such that each CPU write to a NIC send window is atomic and self-defining, i.e., it does not rely on immediately preceding write to determine where the data packet should be sent. Using “address aliasing”, CPU writes to the aliased part of the NIC send window are always directed to the NIC connected to the same switch as the CPU which did the write.
摘要翻译：在分布式多节点计算机系统中，每个交换机在CPU节点，I / O节点和存储器节点之间提供数据分组的路由。每个交换机通过相应的I / O节点连接到网络接口控制器（NIC），用于在网络上传输数据包。每个NIC都是内存映射的。系统地址空间的一部分形成连接到相应交换机的每个NIC的发送窗口。定义用于控制数据分组传输的机制，使得写入NIC发送窗口的每个CPU是原子和自定义的，即，它不依赖于紧接在前的写入，以确定应该发送数据分组的位置。使用“地址别名”，CPU写入NIC发送窗口的别名部分总是被引导到连接到与执行写入的CPU相同的交换机的NIC。

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