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1. 发明授权

US5112765A Method of forming stacked tungsten gate PFET devices and structures resulting therefrom 失效
标题翻译：形成叠层钨栅PFET器件的方法及由此产生的结构
公开(公告)号：US5112765A
公开(公告)日：1992-05-12
申请号：US730736
申请日：1991-07-16
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone , Vincent Vallet
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/822 , H01L21/8238 , H01L21/8244 , H01L23/52 , H01L27/00 , H01L27/092 , H01L27/11
CPC分类号： H01L27/1108 , H01L21/76895 , H01L21/8221 , H01L27/11 , Y10S148/164
摘要： A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.
摘要翻译：提供一种用于制造堆叠半导体结构的制造方法，包括：将第一厚钝化层沉积到基底结构上; 在所述第一厚钝化层中形成暴露至少一个有源区和/或所述多晶硅线之一的第一螺柱开口; 沉积导电材料的第一层以填充第一螺柱开口并限定第一接触螺柱，一些第一接触柱的上部包括PFET器件的栅电极; 平面化结构以使第一接触柱的顶表面与第一厚钝化层的表面共面; 沉积厚的绝缘层以形成PFET器件的栅极电介质，并将其图形化以限定接触开口，以在期望的位置暴露所选择的第一触头柱; 沉积一层多晶硅; 图案化多晶硅层以限定在期望位置处包含第一接触柱的多晶硅焊盘; 选择性地注入以限定PFET器件和互连导体的源区和漏区; 沉积盖层; 在所述第二厚钝化层中沉积形成第二螺柱孔的第二厚钝化层以暴露所述多晶硅焊盘的所述部分和/或所述第一触头柱的部分; 沉积第二层导电材料以限定第二接触柱; 并且平坦化该结构以使第二接触柱的顶表面与第二厚钝化层的表面共面。

2. 发明授权

US5381046A Stacked conductive resistive polysilicon lands in multilevel semiconductor chips 失效
标题翻译：多层半导体芯片中堆叠的导电电阻式多晶硅焊盘
公开(公告)号：US5381046A
公开(公告)日：1995-01-10
申请号：US160470
申请日：1993-12-01
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L29/52 , H01L29/54
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.
摘要翻译：一种半导体结构，用于在CMOS FET技术中制造具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM。该结构由其中具有器件的有源区的半导体衬底形成，并且在其上形成多晶硅线。第一厚钝化层由衬底上方的蚀刻停止层和磷硅酸盐玻璃（PSG）层形成。通过第一厚钝化层的一组第一金属触头柱接触有源区和/或多晶硅线中的至少一个。蚀刻停止层（26）可以是本征多晶硅或Al 2 O 3。第一接触柱的顶表面与第一厚钝化层的顶表面共面。形成在平面结构上的多个多晶硅焊盘与第一触头柱接触。多晶硅焊盘是高电阻性，高导电性或其混合物。在所得结构之上形成第二厚钝化层，其中具有一组第二金属接触柱。第二金属螺柱接触至少一个多晶硅焊盘和/或第一接触螺柱之一。第二接触柱的顶表面与第二厚钝化层的顶表面共面。多个金属焊盘形成在第二厚钝化层之上并且与第二接触柱接触。最终的绝缘膜绝缘并钝化金属焊盘。

3. 发明申请

US20050174180A1 Phase-locked loop 有权
标题翻译：锁相环
公开(公告)号：US20050174180A1
公开(公告)日：2005-08-11
申请号：US10515690
申请日：2003-05-20
申请人： Patrick Mone
发明人： Patrick Mone
IPC分类号： H03L7/093 , H03L7/089 , H03L7/18 , H03L7/00
CPC分类号： H03L7/18 , H03L7/0893 , H03L7/0898
摘要： The present invention relates to an integrated circuit comprising a phase-locked loop (PLL), a charge pump (CP) and calibration means (CAL) for the loop. The invention is characterized in that the calibration means (CAL) comprise:—first means (S1, SHORT for rendering the phase-locked loop (PLL) unstable so that it produces a sinusoidal signal (Vfilt);—second means (COMP) for generating a squared signal (Vs) from the sinusoidal signal (Vfilt);—a logic circuit (LOGIC) for:—determining the frequency of the squared signal (Vs);—comparing said frequency with a desired frequency; and—controlling the charge pump (CP) for correcting the frequency of the squared signal as a function of the desired frequency.
摘要翻译：本发明涉及一种集成电路，其包括用于环路的锁相环（PLL），电荷泵（CP）和校准装置（CAL）。本发明的特征在于，校准装置（CAL）包括： - 用于使锁相环（PLL）不稳定从而产生正弦信号（Vfilt）的第一装置（S 1，SHORT）; - 第二装置（COMP）用于从正弦信号（Vfilt）产生平方信号（Vs）; - 用于：确定平方信号（Vs）的频率的逻辑电路（LOGIC）; - 将所述频率与期望的频率进行比较;以及 - 控制电荷泵（CP），用于根据期望的频率校正平方信号的频率。

4. 发明授权

US5760640A Highly symmetrical bi-direction current sources 失效
标题翻译：高对称双向电流源
公开(公告)号：US5760640A
公开(公告)日：1998-06-02
申请号：US758334
申请日：1996-12-03
申请人： Phillipe Girard , Patrick Mone
发明人： Phillipe Girard , Patrick Mone
IPC分类号： G05F1/618 , G05F3/26 , H03F3/345 , H03L7/089 , G05F1/10
CPC分类号： G05F3/262 , H03L7/0896
摘要： A bi-directional current source which maintains accurate, substantially equal source and sink currents over a large range of output voltages. The current source includes a primary field effect transistor (FET) and two mirroring FET's. It additionally includes at least one operational amplifier for voltage balancing. An optional operational amplifier provides and additional bias voltage and transistor matching optionally provides impedance matching of the supply voltages.
摘要翻译：双向电流源，可在大范围的输出电压下保持精确，基本相等的源极和吸收电流。电流源包括一个主场效应晶体管（FET）和两个镜像FET。它还包括至少一个用于电压平衡的运算放大器。可选的运算放大器提供并且额外的偏置电压和晶体管匹配可选地提供电源电压的阻抗匹配。

5. 发明授权

US5275963A Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom 失效
标题翻译：在多层半导体芯片中形成堆叠的导电和/或电阻多晶硅焊盘的方法及由此产生的结构
公开(公告)号：US5275963A
公开(公告)日：1994-01-04
申请号：US728929
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/10 , H01L21/98
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/53271 , H01L2924/0002 , Y10S257/904
摘要： A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.The present invention also relates to the method for fabricating the same.
摘要翻译：一种半导体结构，包括：其中形成有器件（T1 ...）的有源区（21）和/或在其上形成的多晶硅线（23-1 ...）的半导体衬底（18/19）形成在衬底上方的第一厚钝化层（26/27），其具有一组第一金属触头柱（30-1 ...），其接触至少一个有源区（21）和/或多晶硅线（ 23-1，...）; 所述第一触头柱的表面与所述第一钝化层的表面共面; 形成在与所述第一触头柱接触的所述平面结构上的多个多晶硅焊盘（31-1 ...）多晶硅焊盘是高电阻性，高导电性或其混合物; 形成在所得结构上方的第二厚钝化层（34/35），其具有一组第二金属触头螺柱（37-1 ...），其接触多晶硅焊盘中的至少一个和/或第一触头螺柱中的一个 ; 第二接触柱的表面与第二厚钝化层的表面共面。形成在与第二接触柱接触的第二厚钝化层（34/35）上方的多个金属焊盘（38-1 ...）最后的绝缘膜（39）。本发明的结构可有利地用于在CMOS FET技术中实现具有堆叠多晶硅负载电阻（4D / 2R SRAM单元）的四个器件SRAM单元的芯片中。本发明还涉及其制造方法。

6. 发明授权

US5748125A Digital delay interpolator circuit 失效
标题翻译：数字延迟内插电路
公开(公告)号：US5748125A
公开(公告)日：1998-05-05
申请号：US751286
申请日：1996-11-18
申请人： Carl Cederbaum , Philippe Girard , Patrick Mone
发明人： Carl Cederbaum , Philippe Girard , Patrick Mone
IPC分类号： H03L7/099 , H03K5/00 , H03K5/13 , H03M1/66
CPC分类号： H03K5/133 , H03K2005/00052 , H03L7/099
摘要： Disclosed is a delay interpolator (DI) circuit (or mixer) that can be driven by digital signals. This DI circuit may be incorporated in the loop of a delay interpolator voltage controlled oscillator (DIVCO) circuit. In turn, the digital DIVCO circuit may be inserted in the loop of a phase-locked loop (PLL) circuit for total digitalization thereof. The novel digital delay interpolator circuit (23) has the base structure of the conventional analog delay interpolator circuit except in that, at the first (bottom) level, the two standard NFET input devices which are normally controlled by an analog signal (typically generated by a preceding DAC) are respectively replaced by two arrays (24A, 24B) of smaller NFET devices connected in parallel. The gate of each NFET device of the first array is driven by a bit (c0, c1, . . . ) of the true phase of the digital signal. The gate of each NFET device of the second array is driven by a bit (c0, c1, . . . ) of the complementary phase of the digital signal. For instance, in the loop of a PLL circuit, this digital signal (Sfilt) is generated by the phase detector, then filtered in a digital filter and stored in a thermometer register. As a result, the DAC is no longer necessary thereby saving significant room and energy consumption.
摘要翻译：公开了可以由数字信号驱动的延迟内插器（DI）电路（或混频器）。该DI电路可以并入延迟内插器压控振荡器（DIVCO）电路的回路中。反过来，数字DIVCO电路可以被插入到锁相环（PLL）电路的环路中，用于其数字化。新颖的数字延迟内插器电路（23）具有常规模拟延迟内插器电路的基本结构，除了在第一（底部）电平处，正常由模拟信号控制的两个标准NFET输入装置（通常由前面的DAC）分别由并联连接的较小NFET器件的两个阵列（24A，24B）代替。第一阵列的每个NFET器件的栅极由数字信号真相的位（c0，c1，...）驱动。第二阵列的每个NFET器件的栅极由数字信号的互补相位的位（c0，c1，...）驱动。例如，在PLL电路的环路中，该数字信号（Sfilt）由相位检测器产生，然后在数字滤波器中滤波并存储在温度计寄存器中。因此，DAC不再需要，从而节省大量的房间和能源消耗。

7. 发明授权

US5100817A Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefrom 失效
公开(公告)号：US5100817A
公开(公告)日：1992-03-31
申请号：US729250
申请日：1991-07-12
申请人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
发明人： Carl Cederbaum , Roland Chanclou , Myriam Combes , Patrick Mone
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786
CPC分类号： H01L27/11 , H01L21/8221 , H01L27/1108
摘要： A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

8. 发明授权

US07106140B2 Calibratable phase-locked loop 有权
标题翻译：可校准锁相环
公开(公告)号：US07106140B2
公开(公告)日：2006-09-12
申请号：US10515690
申请日：2003-05-20
申请人： Patrick Mone
发明人： Patrick Mone
IPC分类号： H03L7/00
CPC分类号： H03L7/18 , H03L7/0893 , H03L7/0898
摘要： The subject matter hereof relates to a calibratable phase-locked loop. The calibratable phase-looked loop in an example embodiment comprises a charge pump and calibration means for the loop, wherein calibration means comprises: first means for rendering unstable a stable phase-locked loop so that a sinusoidal signal is provided; second means for generating a squared signal from the so-provided sinusoidal signal; and a logic circuit for determining the frequency of the squared signal and for controlling the charge pump in correcting the frequency of the squared signal as a function of a desired frequency.
摘要翻译：本发明的主题涉及可校准的锁相环。示例实施例中的可校准相位环路包括电荷泵和用于环路的校准装置，其中校准装置包括：用于使稳定的锁相环不稳定的第一装置，从而提供正弦信号; 用于从所提供的正弦信号产生平方信号的第二装置; 以及逻辑电路，用于确定平方信号的频率，并用于控制电荷泵，以校正作为期望频率的函数的平方信号的频率。

9. 发明授权

US6111471A Apparatus and method for setting VCO free-running frequency 失效
标题翻译：设置VCO自由运行频率的装置和方法
公开(公告)号：US6111471A
公开(公告)日：2000-08-29
申请号：US304608
申请日：1999-05-04
申请人： Dominique Bonneau , Vincent Vallet , Patrick Mone
发明人： Dominique Bonneau , Vincent Vallet , Patrick Mone
IPC分类号： H03L7/085 , H03L7/099 , H03L7/10 , H03L7/181 , H03L7/00
CPC分类号： H03L7/099 , H03L7/085 , H03L7/10 , H03L7/181 , H03L2207/06
摘要： The present invention provides an apparatus for setting the free-running frequency of a VCO to a reference frequency. The apparatus comprises frequency range means for setting the VCO within a VCO frequency range among a plurality of VCO frequency ranges. First counting means are operable to count to a first value at the VCO frequency rate and to provide a first ending signal when the first value is reached. Second counting means are operable to count to a second value at the reference frequency rate and to provide a second ending signal when the second value is reached. The second counting means are also operable to provide a reference count value when the first value is reached by the first counting means. A state machine is responsive to the first and second counting means for selecting a VCO frequency range among the plurality of VCO frequency ranges such that the VCO free-running frequency obtained through the selected range gives the closest value to the reference frequency. The state machine comprises means for decrementing the reference count value provided by the second counting means and also means for comparing the decrementation duration to the counting duration of the second counting means. The selection of the best VCO frequency range is based on this comparison.
摘要翻译：本发明提供一种用于将VCO的自由运行频率设置为参考频率的装置。该装置包括用于将VCO设置在多个VCO频率范围内的VCO频率范围内的频率范围装置。第一计数装置可操作地以VCO频率计数到第一值，并且当达到第一值时提供第一结束信号。第二计数装置可操作以在参考频率速率下计数到第二值，并且在达到第二值时提供第二结束信号。当第一计数装置达到第一值时，第二计数装置还可操作以提供参考计数值。状态机响应于第一和第二计数装置，用于选择多个VCO频率范围内的VCO频率范围，使得通过所选范围获得的VCO自由运行频率给出与参考频率最接近的值。状态机包括用于递减由第二计数装置提供的参考计数值的装置，还包括用于将递减持续时间与第二计数装置的计数持续时间进行比较的装置。最佳VCO频率范围的选择是基于此比较。

10. 发明授权

US5783936A Temperature compensated reference current generator 失效
标题翻译：温度补偿参考电流发生器
公开(公告)号：US5783936A
公开(公告)日：1998-07-21
申请号：US758325
申请日：1996-12-03
申请人： Phillipe Girard , Patrick Mone
发明人： Phillipe Girard , Patrick Mone
IPC分类号： G05F3/24 , G05F3/26 , G05F3/30 , H03F1/30 , G05F3/20
CPC分类号： G05F3/262 , Y10S323/907
摘要： A temperature compensated resistance current generator. The generator provides temperature compensated reference current in a digital CMOS environment where resistors with positive temperature coefficients are not available, and where temperature coefficients are large. The current generator has two current sources and a subtraction circuit which subtracts the current from one current source from the current from the other current source to create a primary current. A proportionality circuit multiplies the primary current by a constant to produce the generator output.
摘要翻译：温度补偿电阻电流发生器。发生器在数字CMOS环境中提供温度补偿参考电流，其中具有正温度系数的电阻器不可用，并且其中温度系数较大。电流发生器具有两个电流源和减法电路，它从一个电流源从另一个电流源的电流中减去电流以产生初级电流。比例电路将初级电流乘以常数以产生发电机输出。

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