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1. 发明授权

US06262604B1 Digital synthesizer of signals 失效
标题翻译：信号数字合成器
公开(公告)号：US06262604B1
公开(公告)日：2001-07-17
申请号：US09339100
申请日：1999-06-24
申请人： Pascal Gabet , Jean-Luc de Gouy
发明人： Pascal Gabet , Jean-Luc de Gouy
IPC分类号： H03B1900
CPC分类号： G06F1/0328
摘要： A digital frequency synthesizer comprises means for the generation of the samples of a digital signal to be converted into an analog signal encoded on N bits as a function of a frequency control word, means for the generation of a noise signal encoded on N bits, and a digital-analog converter, the useful signal and the noise signal being truncated to M bits before being added up by an adder. The result of the addition is converted into analog signal form by the digital-analog converter. The generated noise has at least a noise density substantially equal to a law of equiprobability, this density being zero outside a given space. Application especially to direct digital synthesis, for example in the field of radar techniques or that of instrumentation.
摘要翻译：数字频率合成器包括用于产生要转换为以N位编码的模拟信号作为频率控制字的函数的数字信号的采样的装置，用于产生以N位编码的噪声信号的装置，以及数字模拟转换器，有用信号和噪声信号被加法器相加之前被截断为M位。加法的结果由数模转换器转换成模拟信号形式。所产生的噪声至少具有基本上等于等能性定律的噪声密度，该密度在给定空间外为零。特别适用于直接数字合成，例如在雷达技术领域或仪器领域。

2. 发明授权

US6107843A Fractional phase-locked loop coherent frequency synthesizer 失效
标题翻译：分数锁相环相干频率合成器
公开(公告)号：US6107843A
公开(公告)日：2000-08-22
申请号：US70157
申请日：1998-04-30
申请人： Jean-Luc de Gouy , Pascal Gabet
发明人： Jean-Luc de Gouy , Pascal Gabet
IPC分类号： H03L7/183 , H03L7/197 , H03D3/24
CPC分类号： H03L7/1976
摘要： Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.
摘要翻译：现在的单个或多个分数锁相环频率合成器不是相位相干的，因为它们使用具有可变增量K的数字模数P的数字累加器，其状态是已经施加的值的变化的历史的函数在增量上。这种缺乏相位一致性排除了在某些领域（如多普勒雷达）中使用这些合成器。本文提出了一种新颖类型的单相或多分相锁相环频率合成器，其相位相干。这种类型的合成器包括一个或多个增量为1的计数器，其速率由合成器的参考振荡器设置，并且用于相位存储器，以使得在时刻的分数分数比的变化之后可以改变增量或增量与参考振荡器同步。

3. 发明授权

US06384770B1 Linearizing device for a frequency-modulation ramp and its application to a radio altimeter 失效
标题翻译：用于频率调制斜坡的线性化设备及其应用于无线电高度计
公开(公告)号：US06384770B1
公开(公告)日：2002-05-07
申请号：US08467786
申请日：1995-06-21
申请人： Jean-Luc de Gouy , Marc Chelouche , Lionel Fousset
发明人： Jean-Luc de Gouy , Marc Chelouche , Lionel Fousset
IPC分类号： G01S1308
CPC分类号： G01S13/345 , G01S7/35 , G01S7/4008 , G01S13/882
摘要： The invention relates to a device for the linearization of a frequency modulation ramp comprising a voltage controlled oscillator associated with a phase locked-loop. The device comprises a digitally controlled oscillator of which only the most heavily weighted bit is used, and a digital phase comparator receiving, on the one hand, said most heavily weighted bit and, on the other hand, a signal supplied by the voltage controlled oscillator. Application to very high linearity and very high accuracy radio altimeters.
摘要翻译：本发明涉及一种用于线性化频率调制斜坡的装置，其包括与锁相环相关的压控振荡器。该装置包括数字控制的振荡器，其仅使用最重的加权比特，以及一个数字相位比较器，一方面接收所述最重的加权比特，另一方面，由压控振荡器提供的信号适用于非常高的线性度和非常高精度的无线电高度计。

4. 发明授权

US06307492B1 Device to compensate for the non-linearity of an analog/digital converter 失效
标题翻译：用于补偿模拟/数字转换器的非线性的装置
公开(公告)号：US06307492B1
公开(公告)日：2001-10-23
申请号：US09576441
申请日：2000-05-22
申请人： Robert Berranger , Jean-Luc de Gouy
发明人： Robert Berranger , Jean-Luc de Gouy
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/12
摘要： The method consists of the adding of a dither signal of constant amplitude, frequency-modulated by noise, to the signal applied to the input of the converter. An automatic control link is set up between the level of the added interference signal and the signal applied to the input of the converter so that the level of the input signal added to the level of the added interference signal is equal to the level of the full scale signal of the converter. Application to digital communications radio receivers.
摘要翻译：该方法包括将由噪声进行频率调制的恒定幅度抖动信号添加到施加到转换器输入端的信号。在添加的干扰信号的电平和施加到转换器的输入的信号的电平之间建立自动控制链路，使得添加到相加干扰信号的电平的输入信号的电平等于满量程的电平转换器的标度信号。应用于数字通信无线电接收机。

5. 发明授权

US06191657B1 Frequency synthesizer with a phase-locked loop with multiple fractional division 失效
$Frequency synthesizer with a phase-locked loop with multiple fractional division$
标题翻译：频率合成器具有多个分数除法的锁相环
公开(公告)号：US06191657B1
公开(公告)日：2001-02-20
申请号：US07731405
申请日：1991-07-02
申请人： Elie Brunet , Jean-Luc de Gouy , Thierry Ginestet
发明人： Elie Brunet , Jean-Luc de Gouy , Thierry Ginestet
IPC分类号： H03L700
CPC分类号： H03K23/68 , H03K23/667 , H03L7/1976 , H03L2207/10
摘要： A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step Pi×FreF lower than the reference frequency Fref. Each fractional structure is coupled in parallel with said programmable divider to add to said division rank M fractional increments Pi such that the ratio between the frequency Fvco provided by said oscillator and said reference frequency be defined as a function of said increments Pi by the relationship: F vco = ( M ⁢ ∑ 1 n ⁢ P i ) ⁢ F ref .
摘要翻译：频率合成器包括由电压控制振荡器形成的参考时钟控制的单个锁相环，具有可变分频等级M的可编程分频器，相位检测器和环路滤波器。它还包括预定数量n的分数分割结构，每个分数结构实现比参考频率Fref低的频率步长PixFreF。每个分数结构与所述可编程分频器并联耦合以添加到所述分割级M分数增量Pi，使得由所述振荡器提供的频率Fvco与所述参考频率之间的比率被定义为所述增量Pi的函数关系：

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